Source Synchronous Routing Recommendations - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Memory Controller
Table 35.

Source Synchronous Routing Recommendations

Reference Plane
Preferred Layer
Topology
Breakout
Strip line Trace Impedance
Strip Line Trace Spacing (trace edge to neighbor trace
edge)
Trace Lengths
DQ Group Spacing
Series Resistor Rs
Parallel Termination
Length Matching Requirements: within DQS Group
Length Matching Requirements: All DQ/DQS lines to
Clock
Routing Guideline 1
Routing Guideline 2
Routing Guideline 3
Number of Vias
74
Parameter Routing Guideline
Stripline: Route over unbroken ground plane
Microstrip Routing: Route over unbroken power or
ground plane
Stripline
Stripline (stubs needs to be <250 mils)
5 mils x 5 mils Maximum length of breakout region of
500 mils.
45 ohms +/- 15% OR 50 OHMS +/- 15%.
• 5 mils spacing acceptable between pins and
breakout regions
• >12 mils edge to edge between any DQ/DQS
signals
• > 20 mils (edge to edge) maintained from any
other groups
Refer to DIMM DQ/DQS Topology
Figure 39
Spacing from other DQ groups 20 mils minimum
Ω
22.1 +/- 5%
• Single VTT termination of 51.1
(1.25V)
or
• Split terminations of 100 ohms +/- 5% to 2.5V and
100 ohms +/- 5% to ground.
• Place the VTT termination in a VTT island.
+/- 0.050" within DQS group
• The package lengths from Die to Ball provided in
Table 37 must be accounted for when length
matching
• When M_CK is routed on a stripline layer, DQS
should be routed to within +/- 1.5" of its
corresponding M_CK
• When M_CK is routed on a micro-strip layer, DQS
should be routed to within +/- 1.0" of its
corresponding M_CK
Route all data signals and their associated strobes on
the same layer.
Minimize layer changes (two vias or less)
Do not share series terminator resistor packs between
DQ/DQS and Address.
2 (Equal number of vias between DQ and its
respective DQS signal)
Figure 38 and
Ω
+/- 5% to VTT