Intel 80331 Design Manual page 47

Table 8. PCI-X Clock Layout Requirements Summary (Sheet 2 of 2)
Maximum skew for PCI.
Routing Guideline 1.
Routing Guideline 2.
Parameter
1.0 ns.
Point-to-point signal routing needs to be used to keep reflections
low.
Same number of vias and routing layers as all the other clock lines
from the driver to the receiver.
Intel® 80331 I/O Processor Design Guide
PCI-X Layout Guidelines
Routing Guidelines
47