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8.1.4
Flash Memory Support
PBI peripheral bus interface supports 8-, or 16- bit Flash devices.
The PBI provides programmable wait state functionality for peripheral memory windows.
Note: Potentially, programmable wait state functionality could be connected to any peripheral device that
has a deterministic wait state profile. However, data valid and turn-around times need to fit within
parameters provided by programmable wait state profiles to support Flash devices.
Any write transactions issued to a Flash address space window must always represent a single flash
bus data cycle (strb, strh).
The peripheral chip enables, PCE[1:0]#, activate the appropriate Peripheral window when the
address falls within one of the Peripheral address ranges.
Note: By default, bank 0 is enabled with the maximum number of Address-to-Data and Recovery Wait
states. The width of the interface can be strapped for either 8-bit wide Flash or 16-bit wide flash.
Thus, PCE0# is the Peripheral Bus chip enable to be used for booting purposes.
Figure 63
z
Figure 63.
Four MByte Flash Memory System
1.
16-bit wide flash devices requires two latches.
Refer to
Table 72
are based on a 66 MHz internal clock for the PBI interface.
Table 72.
Flash Wait State Profile Programming
1.
Each Wait State Represents 15 ns.
shows how two 8-bit Flash devices interface with 80331through the PBI Interface.
I/O
Processor
A[2:0 ]
AD[22:16]
AD[15:0]
ALE
POE#
PWE#
PCE0#
PCE1#
for the programmable address-to data and recovery wait states. These numbers
Flash Speed
<= 55 ns
<= 115 ns
<= 150 ns
Intel® 80331 I/O Processor Design Guide
1
A[2:0]
A[2:0]
A[20:16]
A[20:16]
A[15:8]
AD[15:8]
A[7:3]
AD[7:3]
Latch
DQ[7:0]
1
Address-to-Data Wait States
4
8
10
Peripheral Local Bus
A[20:0]
OE#
Intel 28F016-70
WE#
16 Mbit Flash
DQ[7:0]
CE#
A[20:0]
OE#
Intel 28F016-70
WE#
16 Mbit Flash
DQ[7:0]
CE#
Recovery Wait States
0
2
2
125
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