Power Delay - Intel 80331 Design Manual

In order to trigger a power fail sequence while the IOP power is still valid operating range, a
comparator circuit such as the one shown in
Figure 67. Power Failure Comparator Circuit
The comparator circuit shown in
to the IOP is still within valid operating conditions. The trip point of the comparator is set using the
ratio of 0.4. This is set with the voltage divider values of the 10 K and the combined value 12.1 K
and 3.01 K 1% resistors. This ratio provides a trip point value of 2.96 V. When the 3.3 V rail falls
below the 2.96 V level, the PWGD signal is forced low. In the CRB, the P_RST# secondary side
reset is tied to the P_RST# pin of the IOP. The P_RST# triggers the power-fail sequence.
9.2.3

Power Delay

The 80331provides a dedicated input pin, PWRDELAY that will be used to distinguish between
and initial power up and a power failure assertion of
a 1.5K resistor.
+3.3V
3.01 K
1%
12.1 K
1%
3
IN+
4
IN–
5
10 K
HYST
1%
6
REF
Figure 67
Intel® 80331 I/O Processor Design Guide
Figure 67 is recommended.
7
V+
MAX921
8
OUT
10 K
GND V–
5%
1 2
is used to trigger a power-fail sequence while the power
This signal should be pulled up with
PWRGD.
Power Delivery
POWER_GOOD
A9229-01
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