Pci 66 Mhz Slot Topology; Pci 66 Mhz Topology; Pci 66 Mhz Slot Table - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
PCI-X Layout Guidelines
Table 20. PCI-X 66 MHz Mixed Mode Routing Recommendations (Sheet 2 of 2)
Trace Length TL3, TL4,
between connectors
Trace Length TL_EM1 from
the first PCI connector to the
embedded device.
Trace Length TL_AD1,
TL_AD2, TL_AD3 from PCI
connector to the Receiver
Length Matching
Requirements:
Number of vias
6.4.14

PCI 66 MHz Slot Topology

Figure 29
slots.
Figure 29.

PCI 66 MHz Topology

Table 21. PCI 66 MHz Slot Table (Sheet 1 of 2)
Reference Plane
Breakout
Motherboard Trace Impedance (microstrip and
stripline)
Add-in card Impedance (microstrip and stripline)
Stripline Trace Spacing
Microstrip Trace Spacing
Group Spacing
Trace Length 1 TL1: From 80331 signal Ball to first
connector
Trace Length TL2 between connectors
60
0.8" minimum - 1.4" maximum
1.0" minimum - 3.5" maximum
0.75" minimum - 1.5" maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines
Four vias maximum
and Table 21 provides routing details for a topology with for an PCI 66 MHz design with
Parameter
Table 8.
AD1
CONN1
TL1 TL2
Routing Guideline for AD
Bus
Route over an unbroken ground plane
5 mils on 5 mils spacing. Maximum length of the
breakout is 500 mils.
50 Ohms +/- 15%
60 Ohms +/- 15%
10 mils, from edge to edge
15 mils, from edge to edge
Spacing from other groups: 25 mils minimum
edge-to-edge
1.0" minimum - 7.0" maximum
0.8" minimum - 1.2" maximum
1.75" minimum - 2.75" maximum
AD2
CONN2
Routing Guideline for
Upper AD Bus
1.0" minimum - 7.0"
maximum