Layout Guidelines For The Peripheral Bus - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Peripheral Local Bus
8.1.5

Layout Guidelines for the Peripheral Bus

This section provides basic layout guidelines for using the Peripheral Bus. Figures below provide
the topology for simulation of clock, control and data lines.
Simulation Scope:
•
Analysis consisted of an 8- or 16-bit address/data bus interfacing with one or two
asynchronous flash devices operating at 66MHz.
•
50 ohm mother board and 60 ohm add-in card stackups were considered
•
Lossy uncoupled transmission lines were used for the simulations
•
Trace spacing were set 3X height of trace over reference plane to avoid crosstalk.
•
The width of the bus (8/16 bits) and the number of flash devices yields six discrete topologies
that were examined.
•
Flash RC128J3A, CPLDs XC9500XL and Octal Latches 74LVC573A were used as loads in
the SI analysis.
126