Reset# Topology; Routing Guidelines For Asynchronous Gtl+ And Miscellaneous Signals; Asynchronous Gtl+ And Miscellaneous Signals - Intel Xeon Design Manual

5.2.2

RESET# Topology

Since the processor does not contain on-die termination for the RESET# input signal, these
additional layout guidelines for the RESET# signal are required. The baseboard trace length from
Processor 0's pin to the termination resistor should be 0 to 1 inch.Follow the same routing
guidelines given for common clock signals listed above in this same section.
Figure 5-3. RESET# Topology
5.3 Routing Guidelines for Asynchronous GTL+ and
Miscellaneous Signals
Table 5-6
Table 5-6. Asynchronous GTL+ and Miscellaneous Signals (Sheet 1 of 2)
Signal Name
A20M#
BINIT#
BR[3:1]#
BR0#
COMP[1:0]
FERR#
IERR#
IGNNE#
INIT#
LINT[1:0]
ODTEN
PROCHOT#
PWRGOOD
SLP#
SM_ALERT#
SM_CLK
Design Guide
VCC_CPU
Processor 0
51 Ω ± 5%
0.1" - 1.0"
enumerates the remainder of the processor signals discussed in this document.
Type
Async GTL+
AGTL+
AGTL+
AGTL+
Analog
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Other
Async GTL+
Async GTL+
Async GTL+
SMBUS (3.3 V)
SMBUS (3.3 V)
System Bus Routing Guidelines
Processor 1
3.0" - 10.1" 3.0" - 10.1"
Processor
Driven By
I/O Type
I ICH3-S
I/O Processor
I Processor
I/O Processor/MCH
I Pull-down
O Processor
O Processor
I ICH3-S
I ICH3-S
I ICH3-S
I Pull-up / Pull-down
O Processor
I External Logic
I ICH3-S
O Processor/Controller
I/O Processor/Controller
MCH
Received By
Processor
Processor
Processor
Processor/MCH
Processor
ICH3-S
External Logic (such as
Baseboard
Management Controller)
Processor
Processor
Processor
Processor
External Logic
Processor
Processor
Controller
Processor/Controller
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