Command Clock Routing; Command Clock Topology; Command Clock Pair Routing Guidelines - Intel Xeon Design Manual

6.3

Command Clock Routing

Only one differential clock pair is routed to each DIMM connector because the MCH only supports
registered DDR DIMMs. All CMDCLK/CMDCLK# termination is on the DIMM modules. Route
each clock and its compliment adjacent to each other. The two complimentary signals (e.g.,
CMDCLK0 and CMDCLK0#) must be length matched to each other within ± 2 mils. Excluding
breakout, the maximum recommended layer changes is one. Ensure that the reference plane does
not change when switching layer.
Table 6-4. Command Clock Pair Routing Guidelines
Signal Group
Topology
Reference Plane
Differential Trace Impedance (Zo)
Nominal Trace Width
Trace Spacing to Complement
Trace Spacing to Other Traces
Trace Length – MCH to DIMM1
Trace Length – MCH to DIMM2
Trace Length – MCH to DIMM3
Trace Length – MCH to DIMM4
MCH Breakout Guidelines
Length Tuning Requirements
Figure 6-7. Command Clock Topology
NOTES:
CMDCLK/CMDCLK# must be matched to within ± 2 mils using package trace length
1.
compensation
2. The total trace length difference of any two CMDCLK/CMDCLK# pairs cannot exceed 4 inches for timing
reasons.
3. For 3-DIMM solutions, treat the CMDCLK3/CMDCLK3# pair as a no connect.
4. Indicated lengths measure from the MCH pin to the DIMM connector pin.
Design Guide
Parameter Intel
CMDCLK[3:0], CMDCLK[3:0]#
Point to point
Ground
100 Ω ± 10%
5 mil
5 mil
20 mil
2.1" to 10.0"
2.1" to 10.0"
2.1" to 10.0"
2.1" to 10.0"
5/5, < 500 mil
CMDCLK to CMDCLK#: ± 2 mil
CMDCLK pair to pair: within ± 4.0 in.
CMDCLK pair to DQS pair: ± 1.75 in.
CMDCLK pair to Source Clocked Signal: ± 2.0 in.
CMDCLK0 & CMDCLK0#
CMDCLK1 & CMDCLK1#
CMDCLK2 & CMDCLK2#
MCH
CMDCLK3 & CMDCLK3#
.
Memory Interface Routing Guidelines
®
E7500
DIMMs
Reference
Figure 6-7
Figure 6-8
Figure 6-8
Figure 6-8
Figure 6-8
Figure 6-8
Figure 6-7
Figure 6-7
Figure 6-7
Figure 6-7
Figure 6-7
Figure 6-6
Figure 6-9
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