Sata Trace Separation; Sata Trace Length Guidelines And Pair Matching; Sata Trace Spacing - Intel EP80579 Manual

Serial ATA (SATA) Interface—Intel
11.2.1

SATA Trace Separation

Figure 101
following separation guidelines for the SATA interface:
• Maintain parallelism between SATA differential signals with the trace spacing
needed to achieve 90 Ω ±10% differential impedance. Deviations will normally
occur due to package breakout and routing to connector pins. Ensure the amount
and length of the deviations are kept as small as possible.
• Use an impedance calculator to determine the trace width and spacing required for
the specific board stackup being used, keeping in mind that the target is a 90
Ω ±10% differential impedance. For the recommended board stackup parameters,
4.5 mil traces with 5.5 mil spacing in stripline, or 4.75 mil traces with 5.25 mil
spacing in microstrip, the results are in approximately 90 Ω ±10% differential trace
impedance.
• Based on simulation data, use 20 mil (stripline) minimum, or 25 mil (microstrip)
minimum spacing between the SATA signal pairs and other signal traces for optimal
signal quality. This helps prevent crosstalk.
.
Figure 101. SATA Trace Spacing
Low -Speed
Non - Periodic Signal
Low -Speed
Non - Periodic Signal
11.2.2

SATA Trace Length Guidelines and Pair Matching

If the trace length of the differential pair is longer than recommended, the high
frequency differential signal will suffer signal attenuation and an increase of rise/fall
time.
SATA signal pair traces must be trace length matched. The difference of two line traces
in a differential pair must be restricted to below 20 mils, but less trace mismatch is
recommended.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
provides an illustration of the recommended trace spacing. Use the
Differential Pair
5.5
20
4.5
Note: This illustration is used to convey trace spacing implementation, it does not
reflect any stackup parameters other than trace width
Differential Pair
5.25
25
4.75
4.75
Note: This illustration is used to convey trace spacing implementation , it does not
reflect any stackup parameters other than trace width
Stripline
Differential Pair
5.5
20
4.5
4.5
Distance in Mils
Microstrip
Differential Pair
5.25
25
4.75
Distance in Mils
Clock /High -Speed
Periodic Clock
20
4.5
Clock /High -Speed
Periodic Clock
25
4.75
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