Display Registers Stored By Address - AMD M56 Reference Manual

A.7

Display Registers Stored by Address

Table A-6 Display Registers Sorted by Address
VGA_SEQUENCER_RESET_CONTROL
VGA_SURFACE_PITCH_SELECT
VGA_MEMORY_BASE_ADDRESS
VGA_DISPBUF1_SURFACE_ADDR
VGA_DISPBUF2_SURFACE_ADDR
VGA_INTERRUPT_CONTROL
VGA_DEBUG_READBACK_INDEX
VGA_DEBUG_READBACK_DATA
VGA_MEM_WRITE_PAGE_ADDR
VGA_MEM_READ_PAGE_ADDR
© 2007 Advanced Micro Devices, Inc.
Proprietary
Register Name
GEN_INT_STATUS
VGA_RENDER_CONTROL
VGA_MODE_CONTROL
VGA_HDP_CONTROL
VGA_CACHE_CONTROL
D1VGA_CONTROL
D2VGA_CONTROL
VGA_STATUS
VGA_STATUS_CLEAR
VGA_INTERRUPT_STATUS
VGA_MAIN_CONTROL
VGA_TEST_CONTROL
CRTC8_IDX
CRTC8_IDX
CRTC8_DATA
CRTC8_DATA
GENFC_WT
GENS1
ATTRDW
ATTRX
ATTRDR
GENMO_WT
GENMO_WT
GENS0
Address
DISPDEC:0x104
DISPDEC:0x300
DISPDEC:0x304
DISPDEC:0x308
DISPDEC:0x30C
DISPDEC:0x310
DISPDEC:0x318
DISPDEC:0x320
DISPDEC:0x328
DISPDEC:0x32C
DISPDEC:0x330
DISPDEC:0x338
DISPDEC:0x340
DISPDEC:0x344
DISPDEC:0x348
DISPDEC:0x34C
DISPDEC:0x350
DISPDEC:0x354
DISPDEC:0x358
DISPDEC:0x35C
DISPDEC:0x38
DISPDEC:0x3B4
DISPDEC:0x3D4
DISPDEC:0x3B4
DISPDEC:0x3D4
DISPDEC:0x3B5
DISPDEC:0x3D5
DISPDEC:0x3B5
DISPDEC:0x3D5
DISPDEC:0x3BA
DISPDEC:0x3DA
DISPDEC:0x3BA
DISPDEC:0x3DA
DISPDEC:0x3C
DISPDEC:0x3C0
DISPDEC:0x3C0
DISPDEC:0x3C1
DISPDEC:0x3C2
DISPDEC:0x3C2
DISPDEC:0x3C2
M56 Register Reference Manual
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