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Bus Interface Registers
USR_DETECTED
AUX_PWR (R)
TRANSACTIONS_PEND (R)
The Device Status register provides information about PCI Express device specific parameters.
Field Name
LINK_SPEED
LINK_WIDTH
PM_SUPPORT
OUR_L0S_EXIT_LATENCY
OUR_L1_EXIT_LATENCY
OUR_PORT_NUM
The Link Capabilities register identifies PCI Express Link specific capabilities.
Field Name
PM_CONTROL
READ_CPL_BOUNDARY (R)
COMMON_CLOCK_CFG
EXTENDED_SYNC
The Link Control register controls PCI Express Link specific parameters.
Field Name
NEGOTIATED_LINK_SPEED
NEGOTIATED_LINK_WIDTH
M56 Register Reference Manual
2-68
3
4
5
LINK_CAP - R - 32 bits - [CFGF0_DEC:0x64] [HIDEC:0x5064]
Bits
Default
3:0
9:4
11:10
14:12
17:15
31:24
LINK_CNTL - RW - 16 bits - [CFGF0_DEC:0x68] [HIDEC:0x5068]
Bits
Default
1:0
3
6
7
LINK_STATUS - R - 16 bits - [CFGF0_DEC:0x6A] [HIDEC:0x506A]
Bits
Default
3:0
9:4
0x0
This bit indicates that the device received an Unsupported Request.
0x0
Devices that require AUX power report this bit as set if AUX power is
detected by the device.
0x0
Endpoints: This bit when set indicates that the device has issued
Non-Posted Requests which have not been completed. Root and
Switch Ports: This bit when set indicates that a Port has issued
Non-Posted Requests on its own behalf (using the Port's own
Requester ID) which have not been completed.
0x1
0=2.5 Gb/s
0x10
0=16 Lanes
0x3
This field indicates the level of ASPM supported on the given PCI
Express Link.
0x1
This field indicates the L0s exit latency for the given PCI Express
Link. The value reported indicates the length of time this Port
requires to complete transition from L0s to L0.
0x2
This field indicates the L0s exit latency for the given PCI Express
Link. The value reported indicates the length of time this Port
requires to complete transition from L0s to L0.
0x0
This field indicates the PCI Express Port number for the given PCI
Express Link.
0x0
This field controls the level of ASPM supported on the given PCI
Express Link. Defined encodings are:
00b Disabled
01b L0s Entry Enabled
10b L1 Entry Enabled
11b L0s and L1 Entry Enabled
0x0
0=64 Byte
1=128 Byte
0x0
This bit when set indicates that this component and the component at
the opposite end of this Link are operating with a distributed com-
mon reference clock. Default value of this field is 0b.
0x0
This bit when set forces the transmission of 4096 FTS ordered sets in
the L0s state followed by a single SKP ordered set
0x1
0=2.5 Gb/s
0x10
This field indicates the negotiated width of the given PCI Express
Link.
Defined encodings are: 000001b X1
000010b X2
001000b X8
010000b X16
All other encodings are reserved.
© 2007 Advanced Micro Devices, Inc.
Description
Description
Description
000100b X4
001100b X12
100000b X32
Proprietary
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