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Bus Interface Registers
Field Name
MSI_MSG_ADDR_HI
MSI Message Upper Address. MSI is assumed to be in 64 bit mode all the time.
MSI_MSG_DATA_64 - RW - 16 bits - [CFGF0_DEC:0x8C] [HIDEC:0x508C]
Field Name
MSI_DATA_64
64-bit MSI Message Data
Field Name
MSI_DATA
MSI Message Data.
PCIE_ENH_ADV_ERR_RPT_CAP_HDR - R - 32 bits - [CFGF0_DEC:0x100] [HIDEC:0x5100]
Field Name
EXT_CAP_ID
CAP_VER
NXT_CAP_OFFSET
Advanced Error Reporting Enhanced Capability header
PCIE_UNCORR_ERR_STATUS - RW - 32 bits - [CFGF0_DEC:0x104] [HIDEC:0x5104]
Field Name
TRN_ERR_STATUS
DLP_ERR_STATUS
PSN_ERR_STATUS
FC_ERR_STATUS
CPL_TIMEOUT_STATUS
CPL_ABORT_ERR_STATUS
UNEXP_CPL_STATUS
RCV_OVFL_STATUS
MAL_TLP_STATUS
ECRC_ERR_STATUS
UNSUPP_REQ_ERR_STATUS
The Uncorrectable Error Status register reports error status of individual error sources on a PCI Express device.
PCIE_UNCORR_ERR_MASK - RW - 32 bits - [CFGF0_DEC:0x108] [HIDEC:0x5108]
Field Name
TRN_ERR_MASK
M56 Register Reference Manual
2-70
MSI_MSG_ADDR_HI - RW - 32 bits - [CFGF0_DEC:0x88] [HIDEC:0x5088]
Bits
31:0
Bits
15:0
MSI_MSG_DATA - RW - 32 bits - [CFGF0_DEC:0x88] [HIDEC:0x5088]
Bits
15:0
Bits
15:0
19:16
31:20
Bits
0
4
12
13
14
15
16
17
18
19
20
Bits
0
Default
0x0
System-specified message upper address.
Default
0x0
Message Data. System specified.
Default
0x0
System-specified message.
Default
0x1
This field is a PCI-SIG defined ID number that indicates the nature
and format of the extended capability.
0x1
This field is a PCI-SIG defined version number that indicates the ver-
sion of the capability structure present.
0x0
This field contains the offset to the next PCI Express capability struc-
ture or 000h if no other items exist in the linked list of capabilities.
Default
0x0
Training Error Status
0x0
Data Link Protocol Error Status
0x0
Poisoned TLP Status
0x0
Flow Control Protocol Error Status
0x0
Completion Timeout Status
0x0
Completer Abort Status
0x0
Unexpected Completion Status
0x0
Receiver Overflow Status
0x0
Malformed TLP Status
0x0
ECRC Error Status
0x0
Unsupported Request Error Status
Default
0x0
Training Error Mask
Description
Description
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
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