Vga Registers; Vga Control/Status Registers - AMD M56 Reference Manual

2.6

VGA Registers

2.6.1

VGA Control/Status Registers

General purpose status VGA
Field Name
VSYNC_SEL_R
(mirror of GENFC_WT:VSYNC_SEL_W)
Feature Control Register (Read)
Field Name
VSYNC_SEL_W
Feature Control Register (Read)
Field Name
GENMO_MONO_ADDRESS_B
VGA_RAM_EN
VGA_CKSEL
ODD_EVEN_MD_PGSEL
VGA_HSYNC_POL
© 2007 Advanced Micro Devices, Inc.
Proprietary
GENFC_RD - R - 8 bits - DISPDEC:0x3CA
Bits Default
3
GENFC_WT - W - 8 bits - [DISPDEC:0x3BA] [DISPDEC:0x3DA]
Bits Default
3
GENMO_WT - W - 8 bits - DISPDEC:0x3C2
Bits Default
0
1
3:2
5
6
0x0 Vertical sync select (read).
0=Normal vertical sync
1=Sync is 'vertical sync' ORed with 'vertical display enable'
0x0 Vertical sync select (write).
0=Normal vertical sync
1=Sync is 'vertical sync' ORed with 'vertical display enable'
0x0 VGA addressing mode.
0=Monochrome emulation, regs at 0x3Bx
1=Color/Graphic emulation, regs at 0x3Dx
0x0 Enables/Disables CPU access to video RAM at VGA aperture.
0=Disable
1=Enable
0x0 Selects pixel clock frequency to use in VGA modes. Used when
CRTC_GEN_CNTL.CRTC_EXT_DISP_EN=0. See
CLOCK_CNTL_INDEX.PPLL_DIV_SEL for non-VGA mode pixel
clock selection.
0=25.1744MHz (640 Pels)
1=28.3212MHz (720 Pels)
2=Reserved
3=Reserved
0x0 This bit is used in odd/even display modes (A/N modes: 0, 1, 2, 3,
and 7). This bit is ignored when either bit GRA06[1] or SEQ4[3] are
enabled.
Used to determine if the VGA aperture maps into the lower (even) or
upper (odd) page of memory.
0=Selects odd (high) memory locations
1=Selects even (low) memory locations
0x0 Determines polarity of horizontal sync (HSYNC) for VGA modes.
0 = HSYNC pulse active high
1 = HSYNC pulse active low
The convention of VGA is to use active low VSYNC for 400 (and 200)
and 480 line modes. Active high is normally used for 350 line modes.
VGA Registers
Description
Description
Description
M56 Register Reference Manual
2-165