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Field Name
ENABLE_PAGE_TABLE
PAGE_TABLE_TYPE
ENABLE_PRIVILEGED_MODE
This register provides control for Context 7 in Page Table Unit 0.
Field Name
PHYSICAL_PAGE_ADDR
This register defines the low end of the translatable address range when using the system context in Page Table Unit 0. This address must be
aligned on a 4k-page boundary - the lower 12 bits will be treated as zero. The mapping range for the system aperture is inclusive between the low
and high addresses.
Field Name
PHYSICAL_PAGE_ADDR
This register defines the high end of the translatable address range when using the system context in Page Table Unit 0. This address must be
aligned on a 4k-page boundary -- the lower 12 bits will be treated as set. The mapping range for the system aperture is inclusive between the low
and high addresses.
Field Name
PROTECTIONS
CONTEXT
LOGICAL_PAGE_ADDR
This register initiates a surface probe sequence in Page Table Unit 0. The page address must be on a 4K-byte boundary. If handling of surface
probes is not enabled, they are reported as always passing. Although both PT units contain this register, only PT0 can process surface probes.
© 2007 Advanced Micro Devices, Inc.
Proprietary
MC_PT0_CONTEXT7_CNTL - RW - 32 bits - MCIND:0x109
Bits
0
1
2
MC_PT0_SYSTEM_APERTURE_LOW_ADDR - RW - 32 bits - MCIND:0x112
Bits
31:0
MC_PT0_SYSTEM_APERTURE_HIGH_ADDR - RW - 32 bits - MCIND:0x114
Bits
31:0
MC_PT0_SURFACE_PROBE - W - 32 bits - MCIND:0x116
Bits
3:0
6:4
31:12
Default
0x0
l1 client will treat addresses as physical if context page table is off
0=off
1=on
0x0
0=flat
1=multi-level
0x0
0=off
1=on
Default
0x0
NOTE: Bits 0:11 of this field are hardwired to ZERO.
Default
0xfff
NOTE: Bits 0:11 of this field are hardwired to ONE.
Default
0x0
bit 0: valid (0x1)
bit 1: read (0x2)
bit 2: write (0x4)
bit 3: privileged (0x8)
verify page address against these protection modes
0x0
other than system context, these assignments are suggestions only --
the driver will determine actual assignments.
0=system
1=gpu
2=host
3=idct
0x0
logical page address to be probed
Memory Controller Registers
Description
Description
Description
Description
M56 Register Reference Manual
2-35
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