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Page 1 AMD-K5 Processor Technical Reference Manual...
Page 2 AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks, and AMD-K5 and K86 are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks and Windows NT is a trademark of Microsoft.
Page 3: Table Of Contents
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Contents 1 Overview 1.1 Features ..........1-2 2 Internal Architecture 2.1 Prefetch and Predecode .
Page 4 4.1.2 Techniques Specific to the AMD-K5 Processor ... 4-3 4.2 Dispatch and Execution Timing ......4-5 4.2.1...
Page 5 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5 Bus Interface 5.1 Signal Overview ........5-2 5.1.1...
Page 6 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.40 PCHK (Parity Status) ......5-101 5.2.41 PEN (Parity Enable) .
Page 7 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.4.5 Locked Cycles ........5-169 Basic Locked Operation .
Page 8 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.3.8 Exceptions and Interrupts in SMM ....6-32 6.3.9 SMM Compatibility with Pentium Processor ... . 6-33 6.4 Clock Control .
Page 9 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Appendix A Compatibility With the Pentium and 486 Processors A.1 Bus Signals ......... A-2 A.1.1 Signal Comparison .
Page 10 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996...
Page 11 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 List of Figures Figure 2-1. Internal Architecture, with Pipeline Stage ... 2-2 Figure 2-2. Pipeline Stage Functions ......2-5 Figure 3-1.
Page 12 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Figure 5-24B. Cache-Writeback and Invalidation Cycle (WBINVD Instruction) Part 2 ....5-186 Figure 5-25. Branch-Trace Message Cycle ..... 5-188 Figure 5-26A.
Page 13 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 List of Tables Table 2-1. ALU Instruction Classes ......2-9 Table 2-2.
Page 14 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-16. Outputs at RESET ....... 5-112 Table 5-17.
Page 15 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Preface This manual describes the technical features of the AMD-K5™ processor, and its dif- ferences from the Pentium processor, at a level of detail suitable for a hardware designer or system-software developer to implement system boards, core system logic, and system software.
Page 16 Pins have pin numbers; sig- nals have signal names. On processors that multiplex signals, pins can carry more than one signal; the AMD-K5 processor, however, does not multiplex signals in this manner.
Page 17 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Writeback—This term refers to two related concepts: • Bus Cycle—A 32-byte burst write cycle to a memory block that has been cached in the modified state. Writebacks can be caused by inquire cycles, internal...
Page 18 • Internal Snooping: These snoops are initiated by the processor (rather than sys- tem logic) during certain types of cache accesses. Both the AMD-K5 and Pen- tium microprocessors support this type of internal snooping for the purpose of detecting self-modifying code. See page 2-22 for details.
Page 19 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Brumm, Penn, and Don Brumm. 80386/80486 Assembly Language Programming. Wind- crest: McGraw-Hill, 1993. Chappell, Geoff. DOS Internals. Reading: Addison-Wesley, 1994. Crawford, John H., and Patrick P. Gelsinger. Programming the 80386. San Francisco: Sybex, 1987.
Page 20 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Pietrek, Matt. Windows Internals. Reading: Addison Wesley, 1993. Richter, Jeffrey. Advanced Windows NT. Redmond: Microsoft Press, 1994. Ro, Sen-Cuo, and Sheau-Chuen Her. i386/i486 Advanced Programming. New York: Van Nostrand Reinhold, 1993. Slater, Michael. Microprocessor-Based Design. Englewood Cliffs: Prentice-Hall, 1989.
Page 21: Overview
XXCAL testing laboratory. The result can be seen in the AMD-K5 processor’s perfor- mance. This performance plus its compatibility with an immense library of existing x86 software make the AMD-K5...
Page 22: Features
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Features Pentium-Processor Standard Compatible with the Pentium (735\90, 815\100) • processor 296-pin socket Compatible with existing Pentium (735\90, 815\100) • processor support infrastructure and system designs Compatible with Pentium, 486, and 386 processor soft- •...
Page 23 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 High-Performance Cache and TLBs • 16-Kbyte instruction cache supports split-line access 8-Kbyte, dual-ported data cache with MESI cache coher- • ency protocol Dual-tagged (both linear and physical tags) • Inquire cycles run in parallel with program cache access •...
Page 24 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Overview...
Page 25: Internal Architecture
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Internal Architecture The RISC design techniques used in the processor’s internal architecture account, in large part, for its high performance. The following sections summarize the processor’s execution pipeline behavior, the hardware aspects of the internal instruc- tion cache and data cache, and the hardware aspects of mem- ory management.
Page 26: Figure 2-1. Internal Architecture, With Pipeline Stage
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Prefetch & Predecode Instruction Cache Linear Tags Branch Prediction Fetch Byte Queue Fast Fast Fast Fast Path Code Path Code Path Code Path Code Decode R.S. R.S. R.S. R.S. R.S. Branch Execute Load Load...
Page 27: Prefetch And Predecode
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Prefetch and Predecode Figure 2-1 (top-left corner) shows the processor’s prefetch and predecode logic being fed with data from the external bus via the memory management unit. Prefetching attempts to keep the instruction cache and prefetch cache filled ahead of the execution pipeline’s fetch requirements.
Page 28: Execution Pipeline
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Execution Pipeline Figure 2-1 shows the relation between the internal logic and the stages of the execution pipeline. Figure 2-2 shows the func- tions of the pipeline stages. The first five stages—Fetch, Decode 1, Decode 2, Execute, and Result—affect throughput performance.
Page 29: Figure 2-2. Pipeline Stage Functions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Fetch Decode 1 Decode 2 Execute Result Retire Fetch a) Calculate Address b) Fetch instruction Predict branch Decode 1 a) Merge into byte queue b) Generate ROPs Decode 2 a) Merge register tags and immediates...
Page 30: Fetch
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 2.2.1 Fetch The processor can fetch up to 16 bytes per clock out of the instruction cache. Fetching begins with the calculation of the linear address for the next instruction along a predicted branch of the x86 instruction stream. The address accesses the instruction cache or, during a miss, the prefetch cache.
Page 31: Decode
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 2.2.2 Decode The two-stage decode logic accepts predicted x86 instruction bytes and their predecode bits from the fetch logic, shifts them into a 16-byte FIFO buffer called the byte queue, merges regis- ter tags and operands, and generates internal RISC operations (ROPs).
Page 32: Execute
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The serializing instructions include OUTx, invalidations (INVD, WBINVD, INVLPG), interrupt returns (IRET, IRETD, RSM), descriptor-table-register and task-register loads (LGDT, LLDT, LIDT, LTR), moves to control or debug registers (MOV to CRx or DRx), model-specific register instructions (RDMSR, WRMSR), and CPUID.
Page 33: Table 2-1. Alu Instruction Classes
ALUs have two-entry reservation stations. Table 2-1 shows the types of ROPs executed by each ALU. Unlike the Pentium pro- cessor, the AMD-K5 processor has few restrictions on the pair- ing of integer instructions needed to use both integer units in parallel.
Page 34: Floating-Point Unit
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Floating-Point Unit The IEEE 854-compatible floating-point unit (FPU) can issue pipelined ROPs from its 2-entry reservation station at the rate of one per clock. One ROP can be issued to either the add or multiply pipeline in each clock, even when the operations are separated by an exchange ROP.
Page 35: Result
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The branch unit receives branch-prediction information from the decoder. If the branch unit executes a branch differently than predicted, it signals the instruction cache, reorder buffer, and decode logic, and it passes the correct information to the branch-prediction array in the fetch stage.
Page 36: Retire
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 2.2.5 Retire The processor implements a real-state (non-speculative) regis- ter file that contains the x86-architecture registers and a real- state 8-Kbyte data cache. While ROPs complete out of order and their results are forwarded to other execution units and to the ROB out of order, their results are always written at retire- ment time to the real-state x86 registers in program order.
Page 37: Cache Organization And Management
Since most x86 instructions access memory, they benefit greatly by being cached, and the faster cache- access time on the AMD-K5 processor is a performance advan- tage. The enabling and operating modes for the caches are software controlled by the CD and NW bits of CR0.
Page 38: Instruction Cache
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The following sections describe the basic architecture and resources of the processor’s internal caches. For information about how the system software and hardware control cache configuration and coherency, see Section 6.2 on page 6-8.
Page 39: Data Cache
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Parts of the current code-segment descriptor are maintained in the instruction cache. This allows the cache to translate logical addresses for branches and other prefetch targets to linear address tags for the incoming cache-line fills.
Page 40: Cache Tags
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 buffer, which resides between the load/store units and the data cache, moves to the real-state data cache or memory. Details on the data-cache storage formats and testing are given in Section 7.4 on page 7-7.
Page 41: Cache-Line Fills
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 dated, many or all of the cached lines may still be valid, but accesses miss in the linear tags and go through the MMU to the physical tags. If an access misses the linear tags but hits in the physical tags, the processor restores the linear tag using the linear address for the access.
Page 42: Cache Coherency
The contents of the processor’s data cache are always real-state. Furthermore, on the AMD-K5 processor, writes to both memory and the data cache are always done in program order, irrespective of the state of the EWBE input sig- nal.
Page 43: Table 2-2. Cache States For Read And Write Accesses
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 2-2. Cache States for Read and Write Accesses Type Cache State Access Cache State After Access Tags Before Access Type Writeback- MESI State Writethrough State invalid single read invalid invalid Read Miss Linear...
Page 44: Table 2-3. Cache States For Snoops, Invalidation, And Replacements
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 2-3. Cache States for Snoops, Invalidation, and Replacements Type of Cache State Cache State After Operation Tags Memory Access Operation Before Writeback- MESI State Operation Writethrough State INV=0 shared writethrough shared or exclu- —...
Page 45: Snooping
2.3.6 Snooping The term snooping commonly refers to at least three different actions, only two of which are supported by the AMD-K5 and Pentium processors: Inquire Cycles—These are bus cycles initiated by external logic that cause the processor to look up an address in its physical cache tags.
Page 46: Table 2-4. Snoop Action
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 2-4. Snoop Action Snooping Action Origin of Instructions Data Type of Access Snoop Instruction Prefetch Data Store Writeback Cache Cache Cache Buffer Buffers External Inquire Cycle Read — — Miss Instruction Cache Read —...
Page 47: Buffers
The AMD-K5 processor, like the 486 processor but unlike the Pentium processor, requires a jump (near or far) after a self- modifying write to clear the prefetch cache. However, both the...
Page 48: Prefetch Cache
EWBE signal is asserted. The AMD-K5 processor has no such real-state write buffer between its data cache and the bus,...
Page 49: Replacement And Invalidation Writeback Buffer
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 buffer, load/store execution units, reservation stations, decode unit, or prefetch cache—are not relevant to an inquire cycle or internal snoop. Such stores are speculative and might never occur, due to a branch misprediction, an interrupt, or other intervening event.
Page 50: Snoop Writeback Buffer
EWBE on writes is to hold additional writes off when the signal is negated. In particular, assertion of EWBE does not permit the AMD-K5 processor to observe a weakly ordered memory-write model, in which writes to cache may...
Page 51: Read/Write Reordering
Nevertheless, the strongly ordered AMD-K5 processor supports high perfor- mance without using weakly ordered memory writes by buffer- ing speculative stores in the store buffer.
Page 52: Paging And The Tlbs
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 2.4.4 Paging and the TLBs The processor supports 4-Kbyte and 4-Mbyte paging with two separate translation lookaside buffers (TLBs) that work in par- allel: 4-Kbyte Pages—A 128-entry, four-way, set-associative TLB that can cover 512 Kbytes of memory space 4-Mbyte Pages—A four-entry, fully-associative TLB that can...
Page 53 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 the TLB reload involves a write to memory to set the PDE Accessed or Dirty bit, a hit during the physical-tag snoop causes the cache line to be invalidated. Details on software configuration for 4-Mbyte paging are given in Section 3.1.2 on page 3-5.
Page 54 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 2-30 Internal Architecture...
Page 55: Software Environment And Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Software Environment and Extensions The AMD-K5 processor is compatible with the instruction set, programming model, memory management mechanisms, and other software infrastructure supported by the 486 and Pen- tium (735\90, 815\100) processors. Operating system and appli- cation software that runs on the Pentium processor can be executed on the AMD-K5 processor without modification.
Page 56: Figure 3-1. Control Register 4 (Cr4)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The sections that follow provide details on the architectural extensions visible to system and application software. Some sections include pseudo-code algorithms for suggested BIOS modifications to support the extensions. Architectural exten- sions visible to debug and test software, such as I/O break- points, are described in Chapter 7.
Page 57: Table 3-1. Control Register 4 (Cr4) Fields
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-1. Control Register 4 (CR4) Fields Mnemonic Description Function Enables retention of designated entries in the 4-Kbyte TLB or 4-Mbyte TLB during invalidations. Global Page Extension 1 = enabled, 0 = disabled. See Section 3.1.3 on page 3-9 for details.
Page 58: Machine-Check Exceptions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.1.1 Machine-Check Exceptions Bit 6 in CR4, the machine-check enable (MCE) bit, controls generation of machine-check exceptions (12h). If enabled by the MCE bit, these exceptions are generated when either of the following occurs:...
Page 59: Figure 3-2. 4-Kbyte Paging Mechanism
However, large data structures such as a video frame buffer or non-paged operating system code can consume many pages and easily overrun the TLB. The AMD-K5 processor accommodates large data structures by allowing the operating system to specify 4-Mbyte pages as well as 4-Kbyte pages, and by implementing a four-entry, fully-associative 4-Mbyte TLB which is separate from the 128-entry, 4-Kbyte TLB.
Page 60: Figure 3-3. 4-Mbyte Paging Mechanism
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 4-Mbyte Page 4-Mbyte Page Directory Byte Page Directory Page Offset Offset Linear Address Figure 3-3. 4-Mbyte Paging Mechanism To enable the 4-Mbyte paging option: 1. Set the Page Size Extension (PSE) bit in CR4 to 1.
Page 61: Figure 3-4. Page-Directory Entry (Pde)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Figure 3-1 and Table 3-1 show the fields in CR4. Figure 3-4 and Table 3-2 show the fields in a page-directory entry. 4-Kbyte page translation differs from 4-Mbyte page translation in the following ways: 4-Kbyte Paging (Figure 3-2)—Bits 31–22 of the linear address...
Page 62: Table 3-2. Page-Directory Entry (Pde) Fields
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-2. Page-Directory Entry (PDE) Fields Mnemonic Description Function For 4-Kbyte pages, bits 31–12 contain the physical base address of a 4-Kbyte page table. Physical Base 31–12 BASE For 4-Mbyte pages, bits 31–22 contain the physical base address Address of a 4-Mbyte page and bits 21–12 must be cleared to 0.
Page 63: Global Pages
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.1.3 Global Pages The processor’s performance can sometimes be improved by making some pages global to all tasks and procedures. This can be done for both 4-Kbyte pages and 4-Mbyte pages. The processor invalidates (flushes) both the 4-Kbyte TLB and the 4-Mbyte TLB whenever CR3 is loaded with the base address of the new task’s page directory.
Page 64: Figure 3-5. Page-Table Entry (Pte)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Physical Base Address Available to Software 11–9 Global Page Size = 0 Dirty Accessed Page Cache Disable Page Writethrough User/Supervisor Write/Read Present (valid) Figure 3-5. Page-Table Entry (PTE) 3-10 Software Environment and Extensions...
Page 65: Table 3-3. Page-Table Entry (Pte) Fields
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-3. Page-Table Entry (PTE) Fields Mnemonic Description Function Physical Base 31–12 BASE The physical base address of a 4-Kbyte page. Address Software may use the field to store any type of information. Available to Soft- 11–9...
Page 66: Virtual-8086 Mode Extensions (Vme)
Without the VME extensions available on the AMD-K5 proces- sor, the operating system controls Virtual-8086 mode access to the IF flag by trapping instructions that can read or write this flag.
Page 67: Hardware Interrupts And The Vif And Vip Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 In addition to these performance problems caused by virtual- ization of the IF flag in Virtual-8086 mode, software interrupts (those caused by INTn instructions that vector through inter- rupt gates) cannot be masked by the IF flag or virtual copies of the IF flag, these flags only affect hardware interrupts.
Page 68 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 protection exception with error code zero, thereby notifying the operating system that the program is now prepared to accept the interrupt. Thus, when VME extensions are enabled, the VIF and VIP bits are set and cleared as follows: VIF—This bit is controlled by the processor and used by the...
Page 69: Figure 3-6. Eflags Register
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 31 30 29 28 27 26 25 24 23 22 Reserved ID Flag Virtual Interrupt Pending Virtual Interrupt Flag Alignment Check Virtual-8086 Mode Resume Flag Nested Task I/O Privilege Level IOPL 13–12 Overflow Flag...
Page 70: Table 3-5A. Instructions That Modify The If Or Vif Flags-Real Mode
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-5A through Table 3-5E shows the effects, in various x86-processor modes, of instructions that read or write the IF and VIF flag. The column headings in this table include the fol- lowing values: PE—Protection Enable bit in CR0 (bit 0)
Page 71: Table 3-5B. Instructions That Modify The If Or Vif Flags-Protected Mode
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-5B. Instructions that Modify the IF or VIF Flags—Protected Mode Handler TYPE IOPL GP(0) ≥ CPL IF ← 0 — — — < CPL — — — — ≥ CPL IF ← 1 —...
Page 72: Table 3-5C. Instructions That Modify The If Or Vif Flags-Virtual-8086 Mode
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-5C. Instructions that Modify the IF or VIF Flags—Virtual-8086 Mode TYPE IOPL GP(0) IF ← 0 — No Change < 3 — — — IF ← 1 — No Change < 3 —...
Page 73: Table 3-5D. Instructions That Modify The If Or Vif Flags-Virtual-8086 Mode Interrupt Extensions (Vme)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-5D. Instructions that Modify the IF or VIF Flags—Virtual-8086 Mode Interrupt Extensions (VME) TYPE IOPL GP(0) IF ← 0 — No Change < 3 VIF ← 0 — No Change IF ← 1 —...
Page 74: Table 3-5E. Instructions That Modify The If Or Vif Flags-Protected Mode Virtual Interrupt Extensions (Pvi)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-5E. Instructions that Modify the IF or VIF Flags—Protected Mode Virtual Interrupt Extensions (PVI) TYPE IOPL GP(0) IF ← 0 — No Change < 3 VIF ← 0 — No Change IF ← 1 —...
Page 75: Bitmap (Irb) Extension
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Software Interrupts In Virtual-8086 mode, software interrupts (INTn exceptions and the Interrupt that vector through interrupt gates) are trapped by the operat- Redirection Bitmap ing system for emulation, because they would otherwise clear (IRB) Extension the real IF.
Page 76: Figure 3-7. Task State Segment (Tss)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 TSS Limit from TR I/O Permission Bitmap (IOPB) (up to 8 Kbyte) Interrupt Redirection Bitmap (IRB) (eight 32-bit locations) Operating System Data Structure Base Address of IOPB 0000h 0000h LDT Selector 0000h 0000h 0000h...
Page 77: Table 3-6. Interrupt Behavior And Interrupt-Table Access
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-6 compares the behavior of hardware and software interrupts in various x86-processor operating modes. It also shows which interrupt table is accessed: the Protected-mode IDT or the Real- and Virtual-8086-mode IVT. The column head- ings in this table include: PE—Protection Enable bit in CR0 (bit 0)
Page 78: Protected Virtual Interrupt (Pvi) Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.1.5 Protected Virtual Interrupt (PVI) Extensions The Protected Virtual Interrupts (PVI) bit in CR4 enables sup- port for interrupt virtualization in Protected mode. In this vir- tualization, the processor maintains program-specific VIF and VIP flags in a manner similar to those in Virtual-8086 Mode Extensions (VME).
Page 79: Model-Specific Registers (Msrs)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Model-Specific Registers (MSRs) The processor supports model-specific registers (MSRs) that can be accessed with the RDMSR and WRMSR instructions when CPL = 0. The following index values in the ECX register access specific MSRs:...
Page 80: Figure 3-9. Machine-Check Type Register (Mctr)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.2.2 Machine-Check Type Register (MCTR) The processor latches the cycle definition and other informa- tion about the current bus cycle in its 64-bit Machine-Check Type Register (MCTR) at the same times that the Machine- Check Address Register (MCAR) latches the cycle address: when a bus-cycle error occurs.
Page 81: Table 3-7. Machine-Check Type Register (Mctr) Fields
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 3-7. Machine-Check Type Register (MCTR) Fields Mnemonic Description Function Set to 1 if the processor was asserting LOCK during the bus LOCK Locked Cycle cycle. M/IO Memory or I/O 1 = memory cycle, 0 = I/O cycle.
Page 82: Hardware Configuration Register (Hwcr)
RDMSR instruction when the ECX register contains the value 83h. For details on the HWCR, see Section 7.1 on page 7-3. New Instructions In addition to supporting all of the 486 processor instructions, the AMD-K5 processor implements the following instructions: CPUID CMPXCHG8B MOV to and from CR4 RDTSC...
Page 83: Cpuid
For detailed instructions on processor and feature identification see the AMD Proces- sor Recognition application note, order# 20734. Table 3-8 outlines the AMD-K5 processor family codes and model codes with the CPU clock frequencies (MHz), bus frequencies (MHz), and P-rating strings (“Pxxx”).
Page 84: Cmpxchg8B
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.3.2 CMPXCHG8B mnemonic opcode description CMPXCHG8B r/m64 0FC7 Compare and exchange 8-byte operand Privilege: Any level Registers Affected: EAX, EBX, ECX, EDX Flags Affected: Exceptions Generated: Real, Virtual-8086, Protected mode—GP(0) for all standard cases. Invalid opcode if destination is a register.
Page 85: Mov To And From Cr4
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.3.3 MOV to and from CR4 mnemonic opcode description MOV CR4,r32 0F22 Move to CR4 from register MOV r32,CR4 0F20 Move to register from CR4 Privilege: CPL = 0 Registers Affected: CR4, 32-bit general-purpose register...
Page 86: Rdtsc
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.3.4 RDTSC mnemonic opcode description RDTSC 0F31 Read time stamp counter Privilege: Selectable by TSD bit in CR4 Registers Affected: EAX, EDX Flags Affected: none Exceptions Generated: Real, Virtual-8086 mode—Invalid Opcode Protected mode—GP (0) if CPL not = 0 when CR4.TSD = 1 The processor’s 64-bit time stamp counter (TSC) increments on each processor clock.
Page 87: Rdmsr And Wrmsr
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.3.5 RDMSR and WRMSR mnemonic opcode description RDMSR 0F32 Read model-specific register (MSR) WRMSR 0F30 Write model-specific register (MSR) Privilege: CPL = 0 Registers Affected: EAX, ECX, EDX Flags Affected: none Exceptions Generated: Real—GP(0) for unimplemented MSR address Virtual-8086 mode—GP(0)
Page 88 CPL is greater than 0, or to access an undefined model-specific register, the proces- sor generates a general-protection exception with error code zero. Model-specific registers, as their name implies, may or may not be implemented by later models of the AMD-K5 processor. 3-34 Software Environment and Extensions...
Page 89 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.3.6 mnemonic opcode description 0FAA Resume execution (exit System Management Mode) Privilege: CPL = 0 Registers Affected: CS, DS, ES, FS, GS, SS, EIP, EFLAGS, LDTR, CR3, EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI...
Page 90: Illegal Instruction (Reserved Opcode)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3.3.7 Illegal Instruction (Reserved Opcode) mnemonic opcode description (none) 0FFF Illegal instruction (reserved opcode) Privilege: Any level Registers Affected: none Flags Affected: none Exceptions Generated: Real, Virtual-8086 mode—Invalid opcode Protected mode—Invalid opcode Protected mode—Invalid opcode This opcode always generates an invalid opcode exception.
Page 91: Performance
The code optimization suggestions in this section cover both general superscalar optimization (that is, techniques common to both the AMD-K5 and Pentium processors) and techniques specific to the AMD-K5 processor. In general, all optimization techniques used for the Pentium processor apply to any wide- issue x86 processor, but wider-issue designs like the AMD-K5 processor have fewer restrictions.
Page 92 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Moreover, future implementations may increase the penal- ties associated with microcoded instructions. Dependencies—Spread out true dependencies to increase the opportunities for parallel execution. Antidependencies and output dependencies do not impact performance. Memory Operands—Instructions that operate on data in memory (load/op/store) can inhibit parallelism.
Page 93: Techniques Specific To The Amd-K5 Processor
Indexed Addressing—There is no penalty for base + index addressing in the AMD-K5 processor. However, future implementations may have such a penalty to achieve a higher overall clock rate. 4.1.2 Techniques Specific to the AMD-K5 Processor Jumps and Loops—JCXZ requires 1 cycle (correctly pre-...
Page 94 Pentium processor's 4 to 9 cycles. Register-based bit-offset forms on the AMD-K5 processor take 5 cycles. If the semantics of the register-based bit-offset form are desired (where the bit off- set can cover a very large bit string in memory), it is better...
Page 95: Dispatch And Execution Timing
Table 4-3 on page 4-19 contains the definitions for the floating-point instructions. The first column in these tables indicates the instruction mnemonic and operand types. The fol- lowing notations are used in the AMD-K5 microprocessor docu- mentation: reg—register mem—memory location imm—immediate value...
Page 96 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The second column contains an identifier with the following format: x_xx_xxxxxxxx_xxx_xxx MODrm[2:0] MODrm[5:3] Opcode Addressing Mode: 0x = register 10 = memory without index 1x = memory with or without index 11 = memory with index...
Page 97 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The x/y value following the ROP type indicates the relative dis- patch and execution cycle of the opcode, in the absence of any conflicts. The format is: x/y[/z] where: x = Dispatch Cycle—The relative cycle in which the ROP is dispatched from decode to the reservation station.
Page 98: Table 4-1. Integer Instructions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 4.2.2 Integer Instructions Table 4-1 shows the execution-unit usage for each integer instruction, along with relative cycle numbers for dispatch and execution of the associated ROPs for the instruction. Table 4-1. Integer Instructions Fastpath or...
Page 99 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing alu1 BT mem, reg 1_1x_10100011_xxx_xxx alu1 BT reg, imm alu1 1_0x_10111010_100_xxx BT mem, imm 1_1x_10111010_100_xxx alu1 BTC reg, reg...
Page 100 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing BTS mem, imm 1_1x_10111010_101_xxx alu1 1/1/3 1/1/2 CALL near relative 0_xx_11101000_xxx_xxx 1/1/2 CALL near reg 0_0x_11111111_010_xxx CALL near mem...
Page 101 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing fpfill 1/1/4 IMUL reg, reg, imm 0_0x_011010x1_xxx_xxx fmul 1/1/4 IMUL AX, AL, mem fpfill 1/2/4 0_1x_11110110_101_xxx fmul 1/2/4 IMUL EDX:EAX, EAX, mem...
Page 102 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing MOV reg, mem 0_1x_1000101x_xxx_xxx MOV mem, reg 0_10_1000100x_xxx_xxx MOV mem, reg 0_11_1000100x_xxx_xxx 1/2/3 (base + index addressing) MOV AL/AX/EAX, mem...
Page 103 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing NOT mem 0_1x_1111011x_010_xxx 1/1/3 OR reg, reg 0_0x_000010xx_xxx_xxx OR reg, mem 0_1x_0000101x_xxx_xxx OR mem, reg 0_1x_0000100x_xxx_xxx 1/1/3 OR AL/AX/EAX, imm...
Page 104 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing ROL reg, 1 0_0x_1101000x_000_xxx alu1 ROL mem, 1 0_1x_1101000x_000_xxx alu1 1/1/3 ROL reg, imm alu1 0_0x_1100000x_000_xxx ROL mem, imm...
Page 105 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing SETcc mem 1_1x_1001xxxx_xxx_xxx 1/2/3 SHL reg, 1 alu1 0_0x_1101000x_1x0_xxx SHL mem, 1 0_1x_1101000x_1x0_xxx alu1 1/1/3 SHL reg, mem 0_0x_1100000x_1x0_xxx...
Page 106 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing SHR mem, CL 0_1x_1101001x_101_xxx alu1 1/1/3 alu1 SHRD reg, reg, imm 1_0x_10101100_xxx_xxx alu1 alu1 SHRD mem, reg, imm 1_1x_10101100_xxx_xxx...
Page 107: Integer Dot Product Example
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-1. Integer Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcode Unit Timing XCHG reg, reg 0_0x_1000011x_xxx_xxx XCHG mem, reg 1/1/2 0_1x_1000011x_xxx_xxx XOR reg, reg 0_0x_001100xx_xxx_xxx XOR reg, mem 0_1x_0011001x_xxx_xxx XOR mem, reg...
Page 108: Table 4-2. Integer Dot Product Internal Operations Timing
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-2 shows the timing of internal operations from dis- patch to retire of each ROP for nearly two iterations of this loop. All memory accesses are assumed to hit in the cache. EVEN_ARRAY_SIZE is set to 20.
Page 109: Floating-Point Instructions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 4.2.4 Floating-Point Instructions Floating-point ROPs are always dispatched in pairs to the FPU reservation station. The first ROP conveys the lower halves of the A and B operands, and it always has the fpfill ROP type.
Page 110: Table 4-3. Floating-Point Instructions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-3. Floating-Point Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcoded Unit Timing fpfill 1/2/5 FADDP ST(i), ST 0_0x_11011110_000_xxx fadd 1/2/5 fpfill 1/2/4 FCHS 0_0x_11011001_100_xxx fchs 1/2/4 fpfill 1/2/4 FCOM ST(i) 0_0x_11011x00_010_xxx...
Page 111 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-3. Floating-Point Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcoded Unit Timing fpfill 1/3/7 FICOM int_16 0_1x_11011110_010_xxx fadd 1/3/7 fpfill 2/7/9 2/7/9 fpfill 1/3/7 FICOM int_32 0_1x_11011010_010_xxx fadd 1/3/7 fpfill 2/7/9...
Page 112 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-3. Floating-Point Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcoded Unit Timing fpfill 1/2/5 FIST int_16 0_1x_11011111_010_xxx fadd 1/2/5 1/5/6 fpfill 1/2/5 FIST int_32 0_1x_11011011_010_xxx fadd 1/2/5 1/5/6 fpfill 1/2/5 FISTP int_16...
Page 113 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-3. Floating-Point Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcoded Unit Timing fpfill 1/3/7 FISUBR int_32 0_1x_11011010_101_xxx fadd 1/3/7 fpfill 2/7/10 fadd 2/7/10 FLD real_32 fpfill 1/3/5 0_1x_11011001_000_xxx 1/3/5 FLD real_64...
Page 114 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-3. Floating-Point Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcoded Unit Timing fpfill 1/2/8 FSCALE 0_0x_11011001_111_xxx fadd 1/2/8 fpfill 1/2/4 FST real_32 0_1x_11011001_010_xxx 1/2/4 1/2/5 fpfill 1/2/4 FST ST(i) 0_0x_11011101_010_xxx 1/2/4...
Page 115 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 4-3. Floating-Point Instructions (continued) Fastpath or Execution Instruction Mnemonic Opcode Format Microcoded Unit Timing fpfill 1/2/5 FSUBR ST, ST(i) 0_0x_11011000_101_xxx fadd 1/2/5 fpfill 1/2/5 FSUBR ST(i), ST 0_0x_11011100_101_xxx fadd 1/2/5 FSUBR real_32 0_1x_11011000_101_xxx...
Page 116 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 4-26 Performance...
Page 117: Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Bus Interface This chapter describes two closely related subjects, bus signals (Sections 5.1 and 5.2) and the bus-cycle protocols implemented with those signals (Sections 5.3 and 5.4). These sections describe only the architectural characteristics and functions of the signals and bus cycles.
Page 118: Figure 5-1. Signal Groups
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Signal Overview The signals on the AMD-K5 processor are compatible with the comparable signals on the Pentium (735\90, 815\100) processor 296-pin socket. Appendix A gives a complete list of hardware and software issues relating to this compatibility. The follow- ing figures and tables summarize the characteristics and behavior of the AMD-K5 processor’s signals:...
Page 119 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Clock (BF1–BF0) AHOLD BRDY BOFF BRDYC BREQ Data Arbitration D63–D0 HLDA DP7–DP0 HOLD Data PCHK Parity A20M A31–A3 Address EADS Inquire Address HITM Cycles ADSC Parity APCHK BE7–BE0 AMD-K5 FERR Floating-Point Processor EWBE Cycle...
Page 120: Signal Characteristics
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.1.1 Signal Characteristics Table 5-1. Summary of Signal Characteristics Sampled (Input) or Internal Signal Type Floated Resistor Asserted (Output) Every clock. A20M Output: From ADS until last expected BRDY of the bus AHOLD +1, cycle.
Page 121 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-1. Summary of Signal Characteristics (continued) Sampled (Input) or Internal Signal Type Floated Resistor Asserted (Output) BOFF +1 or From ADS until the last expected BRDY of the bus cycle. HLDA Output (single transfer): From one clock after ADS until BRDY.
Page 122 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-1. Summary of Signal Characteristics (continued) Sampled (Input) or Internal Signal Type Floated Resistor Asserted (Output) Every clock. IGNNE Every clock. Rising-edge-triggered. Recognized at next INIT instruction boundary. Every clock. Level-sensitive. Recognized at next instruc- tion boundary.
Page 123: Conditions For Driving And Sampling Signals
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-1. Summary of Signal Characteristics (continued) Sampled (Input) or Internal Signal Type Floated Resistor Asserted (Output) BOFF +1 or SCYC From ADS until last expected BRDY of the bus cycle. HLDA Every clock. Falling-edge-triggered. Recognized at next pullup instruction boundary.
Page 124: Table 5-2. Conditions For Driving And Sampling Signals
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-2. Conditions for Driving and Sampling Signals Conditions under which signals are meaningfully driven or sampled Reset, Arbitration Bus Cycles or Cache Accesses States and Modes Debug Signal Bus Arbitration AHOLD — BOFF —...
Page 125 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-2. Conditions for Driving and Sampling Signals (continued) Conditions under which signals are meaningfully driven or sampled Reset, Arbitration Bus Cycles or Cache Accesses States and Modes Debug Signal Cache Control CACHE 38 37 25 25 25 25 16...
Page 126 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-2. Conditions for Driving and Sampling Signals (continued) Conditions under which signals are meaningfully driven or sampled Reset, Arbitration Bus Cycles or Cache Accesses States and Modes Debug Signal External Interrupts, Interrupt Acknowledgments, and Reset...
Page 127 PRDY is asserted, it is latched and acted upon after PRDY is negated. 23. During AHOLD, the system must prevent other bus masters from locking the same address that the AMD-K5 processor is locking. 24. Different than the Pentium processor, which ignores STPCLK in this state.
Page 128 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 30. The first code fetch after register initialization during INIT or RESET does not occur if AHOLD, BOFF, or HLDA is asserted. 31. PRDY is asserted either when R/S goes Low or when the Test Access Port (TAP) instruction, USEHDT, is executed. In the latter case, R/S is watched for a Low-to-High transition, which takes the processor out of the Hardware Debug Tool (HDT) mode.
Page 129: External Interrupts
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.1.3 External Interrupts Interrupts and exceptions are often differentiated in x86 docu- mentation as follows: an interrupt is the assertion of a hard- ware input signal and an exception is a software event, such as an invalid opcode or execution of an INTn instruction.
Page 130 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The processor writes (pushes) its current state onto the stack prior to entering the service routine for exceptions and for BUSCHK, SMI, NMI, and INTR interrupts. Because of these writes, the state of EWBE affects the processor’s response to such interrupts and exceptions.
Page 131 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 INTR Interrupts—The processor disables INTR interrupts during all software interrupts (that is, INTn instructions that vector through interrupt gates or through task gates that reference a TSS with IF cleared in its EFLAGS image). It does this by automatically clearing the IF bit in EFLAGS.
Page 132: Table 5-3. Summary Of Interrupts And Exceptions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-3. Summary of Interrupts and Exceptions Priority Description Type Acknowledgment Sampling Vector Point of Interruptibility INTn instruc- tions and all exceptions internal 0-255 none Entry to service routine. other software exceptions interrupt level-sensitive...
Page 133: Bus Signal Compatibility With Pentium Processor
FLUSH operation will then continue; any writebacks that com- pleted before BOFF was asserted are not affected. 5.1.4 Bus Signal Compatibility with Pentium Processor The differences in bus signal functions between the AMD-K5 and Pentium processors are described in Section A.1 on page A-2. Signal Descriptions The following pages describe each signal in detail.
Page 134: A20M (Address Bit 20 Mask)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.1 A20M (Address Bit 20 Mask) Input Summary Assertion of A20M causes the processor to clear bit 20 of the A31–A3 address bus to 0 prior to accessing the cache or mem- ory in Real mode. The clearing of address bit 20 bit maps addresses above 1 Mbyte to addresses below 1 Mbyte.
Page 135 The AMD-K5 processor simply ignores A20M except when the processor runs in Real mode. The AMD-K5 processor applies A20M masking to its linear cache tags, through which all programs access the caches. Thus, assertion of A20M affects all program-generated cache...
Page 136: A31–A3 (Address Bus)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.2 A31–A3 (Address Bus) A31–A5 Bidirectional, A4–A3 Output Summary A31–A3 carries the physical address for the current bus cycle. The processor drives addresses on A31–A3 during memory and I/O cycles, and cycle definition information during special bus cycles.
Page 137: Table 5-4. Address-Generation Sequence During Bursts
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 addresses on A31–A3. In this manner, BE7–BE0 replace the function of address bits A2–A0, which do not exist. When the processor drives burst reads it drives the starting address on A31–A3 (which is the address of the quadword that contains the instruction or data required) and it drives BE7–...
Page 138 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The EADS input defines the beginning of the inquire cycle and validates the input address on A31–A5. The AP input carries the even parity bit for the A31–A5 address. The APCHK output indicates a parity error for the inquire cycle address on A31–A5.
Page 139 See the data sheet for details. Unlike the Pentium processor, pipelined address-data transac- tions are not supported by the AMD-K5 processor. Thus, the NA input has no effect on the processor’s address bus. NA only affects the sampling time for the KEN and WB/WT inputs.
Page 140: Ads (Address Strobe)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.3 ADS (Address Strobe) Output Summary The processor asserts ADS to specify the beginning of a mem- ory or I/O bus cycle, or a cache writeback to memory. The sig- nal validates the processor’s address and cycle definition signals and it can be used by system logic to enable accesses to memory and I/O.
Page 141 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 entries, the processor uses a pseudo-random algorithm to select a line for replacement. If the selected line is cached in the modified state, it must be written back to memory. In this case, the order of events is: 1.
Page 142 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 bus masters, thus intervening temporarily in the processor’s sequential operations. If BOFF is asserted while ADS is asserted, ADS remains Low (floats asserted). System logic must consider this when inter- preting the state of ADS after negating BOFF. In the next clock after BOFF is negated, the processor may reassert ADS to restart a cycle if a cycle was aborted by the assertion of BOFF.
Page 143: Adsc (Address Strobe Copy)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.4 ADSC (Address Strobe Copy) Output Summary ADSC is an identical copy of ADS. In systems that would other- wise place large capacitive loads on ADS, the ADSC output can be used instead of ADS to distribute loads, thereby increasing response time.
Page 144: Ahold (Address Hold)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.5 AHOLD (Address Hold) Input Summary System logic can assert AHOLD to obtain control of the bidi- rectional A31–A3 address bus and AP address parity signal to drive one or more inquire cycles to the processor.
Page 145 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 When the processor releases control of A31–A3 and AP in response to AHOLD, the processor still maintains control of the remaining signals on the bus so that it can (a) finish driving a bus cycle it may have begun before AHOLD was asserted, and (b) drive a writeback if an inquire cycle hits a modified line in the processor’s data cache.
Page 146 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 BREQ asserted continuously. For a list of signals recognized while AHOLD is asserted, see Table 5-2 on page 5-8. The processor may again drive its own cycles with ADS as early as one clock after system logic negates AHOLD. Before negat-...
Page 147: Ap (Address Parity)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.6 AP (Address Parity) Bidirectional Summary AP carries the even parity bit for cache line addresses driven and sampled on A31–A5. The processor drives AP when it drives an address for a read or write cycle. The processor sam- ples AP during inquire cycles in order to drive the APCHK out- put.
Page 148: Apchk (Address Parity Check)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.7 APCHK (Address Parity Check) Output Summary The processor asserts APCHK if an even-parity error occurs on A31–A5 during an inquire cycle. Driven The processor drives APCHK for one clock, two clocks after system logic asserts EADS with an inquire address.
Page 149: Be7–Be0 (Byte Enables)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.8 BE7–BE0 (Byte Enables) Output Summary The eight bits of BE7–BE0, when cleared to 0, validate the eight bytes driven on D63–D0. In this way, BE7–BE0 expands on the function of address bits A2–A0, which do not exist on the A31–A3 address bus.
Page 150: Table 5-5. Relation Of Be7-Be0 To Other Signals
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 logic drives KEN with the first BRDY. If system logic negates KEN, it must return as a single transfer only the bytes speci- fied on BE7–BE0. If system logic asserts KEN, it must ignore BE7–BE0 during all transfers of the burst and return all eight...
Page 151: Table 5-6. Encodings For Special Bus Cycles
1. For all special bus cycles, D/C = 0, M/IO = 0 and W/R = 1. System logic must return BRDY in response to this cycle. 2. The message in a branch-trace message special bus cycle is different in the AMD-K5 and Pentium processors.
Page 152: Table 5-7. Processor-To-Bus Clock Ratios
Reserved Notes: 1. The default processor-to-clock ratios are shown in Table 5-7. Specific models of the AMD-K5 processor may implement different ratios for the High and Low values of BF. For authorative information, see the data sheet for each AMD-K5 processor model.
Page 153: Boff (Backoff)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.10 BOFF (Backoff) Input Summary When system logic asserts BOFF, the processor floats the bus and continues to float it until BOFF is negated. If the processor is driving a bus cycle when BOFF is asserted, the cycle is aborted and restarted after BOFF is negated.
Page 154: Table 5-8. Outputs Floated When Boff Is Asserted
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 BOFF provides the fastest response of the three bus-hold inputs. Because of its ability to help resolve deadlock prob- lems, it is required in almost all systems with multiple-caching masters. In such designs, system logic typically drives separate BOFF signals to each bus master in the system.
Page 155 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 it wants. The processor has no way of breaking the hold. While the processor is backed off, it continues to execute out of its instruction and data caches, if possible. If it can no longer operate out of its caches, it holds BREQ asserted continuously.
Page 156 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 If BOFF is asserted when BUSCHK is asserted, BOFF is recog- nized and BUSCHK is ignored. For a list of signals recognized while BOFF is asserted, see Table 5-2 on page 5-8. 5-40 Bus Interface...
Page 157: Brdy (Burst Ready)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.11 BRDY (Burst Ready) Input Summary For bus cycles that transfer data, system logic must assert BRDY to indicate that it has received a data transfer on D63– D0 during a write and to indicate that it has placed valid data on D63–D0 during a read.
Page 158 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The processor samples BRDY during all types of bus cycles, including the following: Single-transfer reads Single-transfer writes (including cache writethroughs) Burst reads (cache line fills) Burst writebacks Special bus cycles Interrupt acknowledge cycles The number of BRDYs expected by the processor depends on...
Page 159 PCHK—Two clocks after every BRDY for writes. In addition to the above uses of BRDY on the 486 processor, BRDY on the AMD-K5 and Pentium processors is used for both single-transfer and burst cycles, and it terminates special bus cycles.
Page 160: Brdyc (Burst Ready)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.12 BRDYC (Burst Ready) Input Summary BRDYC is an identical copy of BRDY, except that BRDYC has an internal pullup resistor whereas BRDY does not. In systems that would otherwise place large capacitive loads on BRDY, the BRDYC output can be used in place of BRDY to distribute loads, thereby increasing response times.
Page 161: Breq (Bus Request)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.13 BREQ (Bus Request) Output Summary The processor asserts BREQ to indicate that it is either driving a cycle on the bus, performing certain types of cache accesses, or needs access to the bus in order to continue operating.
Page 162: Buschk (Bus Check)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.14 BUSCHK (Bus Check) Input Summary System logic can assert BUSCHK if it determines that the cur- rent bus cycle has or will have any type of error. In response, the processor stores information about the aborted bus cycle and (optionally) generates a machine check exception.
Page 163 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Details Bus cycle errors such as parity can be reported to the processor on BUSCHK if this reporting is not done on NMI. The BUSCHK signal is not used in most PC systems, although higher-end sys- tems may find uses for it in special situations.
Page 164 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 BUSCHK is asserted and recognizes latched interrupts in prior- ity order when BUSCHK is negated. The MCE bit in CR4, which enables machine check exceptions during BUSCHK, also enables machine check exceptions dur- ing data parity errors that are indicated on PCHK while PEN is asserted.
Page 165: Cache (Cacheable Access)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.15 CACHE (Cacheable Access) Output Summary The processor drives CACHE to specify that the current bus cycle is a burst cycle. If CACHE is asserted for a read cycle, the cycle is a four-transfer burst and fills a cache line. If CACHE is asserted for a write cycle, the cycle is a four-transfer burst writeback of a modified cache line.
Page 166 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 during write hits to shared cache lines and during write misses, but writethroughs are driven as single transfers of 1 to 8 bytes. CACHE is not asserted during writethroughs. CACHE is partially determined by the PCD bit maintained by...
Page 167: Table 5-9. Mesi-State Transitions For Reads
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 CACHE is not asserted for the following types of memory reads (M/IO = 1): Locked reads (that is, while LOCK is asserted) TLB reads Any read with PCD asserted (PCD is a factor in determining the state of CACHE) Table 5-9.
Page 168: Clk (Bus Clock)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.16 CLK (Bus Clock) Input Summary CLK, in conjunction with the state of BF at RESET, determines the frequency of the processor’s internal clock. Sampled The processor always samples CLK. The clock must have begun oscillating prior to the assertion of RESET during power-up.
Page 169: D/C (Data Or Code)
(indicating a code access) or its load/store logic (indicating a data access). In the AMD-K5 processor, code accesses can be done specula- tively, but data accesses are not. Only data (not code) can be...
Page 170 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 During special bus cycles, the processor drives D/C = 0, M/IO = 0, and W/R = 1. The cycles are then differentiated by BE7–BE0 and A31–A3. 5-54 Bus Interface...
Page 171: D63–D0 (Data Bus)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.18 D63–D0 (Data Bus) Bidirectional Summary The processor drives and samples up to eight bytes on D63–D0 during memory or I/O accesses. System logic must decode the source and destination of these transfers using the address bus and various control signals.
Page 172: Table 5-10. Relation Between D63-D0, Be7-Be0, And Dp7-Dp0
If memory reads, memory writes, or I/O reads are misaligned, the Pentium processor transfers the highest-addressed portion followed by the lowest-addressed portion. The AMD-K5 proces- sor runs such cycles in the opposite order from the Pentium processor. I/O writes, however, are performed in the same order on both processors.
Page 173: Dp7–Dp0 (Data Parity)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.19 DP7–DP0 (Data Parity) Bidirectional Summary DP7–DP0 carry the even-parity bits for each byte driven and sampled on the D63–D0 data bus. While DP7–DP0 are outputs, system logic can use the signals to check parity. While DP7–...
Page 174: Eads (External Address Strobe)
AHOLD is negated, EADS is not recognized. If EADS is asserted on the same clock that HOLD is negated, both the AMD-K5 and the Pentium processors recognize this as a valid inquire cycle and process it correctly. However, if EADS is...
Page 175 (c) automatic bus watching, in which a caching device con- stantly compares addresses being driven by any other device on the address bus with its own cached addresses. The AMD-K5 and Pentium processors only support the first two types of snooping, not the third.
Page 176 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 negated one clock after the last BRDY of the writeback, at which time another EADS can be asserted. If AHOLD is held asserted throughout an inquire cycle, system logic must latch the inquire cycle address when EADS is asserted.
Page 177 HIT and HITM change state two clocks after EADS, and EADS can be asserted in the same clock in which HITM is negated. The AMD-K5 processor does not sample EADS in the clock after a valid EADS assertion. Signal Descriptions...
Page 178: Ewbe (External Write Buffer Empty)
EWBE is asserted. Details All writes on the AMD-K5 processor—whether to cache, mem- ory, or I/O—are performed in program order, regardless of the state of EWBE. The only effect of EWBE on writes is to hold off additional writes when the signal is negated.
Page 179 EWBE is asserted. If system logic implements memory-mapped I/O as non-cache- able memory (the standard method), EWBE on the AMD-K5 processor has the same effect on writes to memory-mapped I/O as does EWBE on the Pentium processor—neither processor reorders reads ahead of writes.
Page 180: Ferr (Floating-Point Error)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.22 FERR (Floating-Point Error) Output Summary The processor asserts FERR to report the occurrence of an unmasked floating-point exception resulting from the execu- tion of a floating-point instruction. This signal is provided to allow the system logic to handle this exception in a manner consistent with IBM-compatible PC/AT systems.
Page 181: Flush (Cache Flush)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.23 FLUSH (Cache Flush) Input Summary FLUSH causes the processor to writeback (if necessary) and invalidate each line in its data and instruction caches. The pro- cessor generates a flush-acknowledge special bus cycle at the end of the entire operation.
Page 182 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 use the Flush-Acknowledge special bus cycle to initiate such action. Entry into SMM may require the assertion of FLUSH. If the SMM physical memory space overlaps physical main memory that is cacheable, FLUSH must be asserted with SMI (the FLUSH will be performed first, because it is a higher-priority interrupt).
Page 183 The Float-Test mode can only be exited by assert- ing RESET again. On the AMD-K5 and Pentium processors, FLUSH is an edge- triggered interrupt. On the early 486 processors, however, the signal is a level-sensitive input.
Page 184: Frcmc (Functional-Redundancy Check Master/Checker)
Errors detected by the checker are reported on the checker’s IERR output. On the AMD-K5 processor, the IERR output is reserved solely for functional-redundancy checking; no other errors are reported on that output.
Page 185 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 their signals are tied together so that they run the same pro- gram. The Functional-Redundancy Checking mode can only be exited by the assertion of RESET. Functional-redundancy checking cannot be done in the Hardware Debug Tool (HDT) mode.
Page 186: Hit (Inquire-Cycle Hit)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.25 HIT (Inquire-Cycle Hit) Output Summary The processor asserts HIT to indicate that an inquire cycle hit a valid line in the processor’s instruction or data cache. Driven The processor drives HIT every clock. The signal changes state two clocks after the assertion of EADS and retains that state until two clocks after the next EADS.
Page 187: Table 5-11. Mesi-State Transitions For Inquire Cycles
WT = 1. This may cause the line to be cached in the exclusive state in two separate caches if the system supports other cach- ing masters. In such cases, the AMD-K5 processor asserts HIT and caches the line in the shared state or does not cache it, depending on the state of the INV signal.
Page 188: Hitm (Inquire Cycle Hit To Modified Line)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.26 HITM (Inquire Cycle Hit To Modified Line) Output Summary The processor asserts HITM to indicate that an inquire cycle hit a modified line in the processor’s data cache. If this occurs, the processor writes the line back to memory during or after the bus-hold tenure, depending on which signal is holding the processor off the bus.
Page 189 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The processor drives writebacks by asserting ADS and either reusing the inquire cycle address (if AHOLD is held asserted throughout the writeback) or driving the address itself (if AHOLD is negated for the writeback, or if BOFF or HOLD was used to obtain the bus).
Page 190: Table 5-12. Outputs Floated When Hlda Is Asserted
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.27 HLDA (Bus-Hold Acknowledge) Output Summary When system logic asserts HOLD, the processor completes any in-progress bus cycle, floats its cycle-driving outputs, and asserts HLDA as an acknowledgment. While HLDA is asserted, another bus master can drive cycles on the bus, including inquire cycles to the processor.
Page 191 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Unlike BOFF, the assertion of HOLD does not abort an in- progress cycle. If the processor is not driving a bus cycle when HOLD is asserted, the bus master asserting or causing the assertion of HOLD can begin driving its first bus cycle in the clock after HLDA is asserted, which occurs two clocks after HOLD is asserted.
Page 192: Hold (Bus-Hold Request)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.28 HOLD (Bus-Hold Request) Input Summary When system logic asserts HOLD, the processor completes any in-progress bus cycle, floats its cycle-driving outputs, and asserts HLDA to acknowledge the HOLD. Sampled and The processor samples HOLD every clock. It acknowledges...
Page 193 However, if EADS is asserted on the clock fol- lowing the negation of HOLD, the AMD-K5 processor does not recognize this as a valid inquire cycle.
Page 194: Ierr (Internal Error)
No other errors are reported with IERR. Unlike the Pentium processor, the AMD-K5 processor does not report parity errors on IERR for every cache or TLB access. Instead, the AMD-K5 processor fully tests cache parity during the built-in self test (BIST), which is invoked by asserting INIT during RESET.
Page 195: Ignne (Ignore Numeric Error)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.30 IGNNE (Ignore Numeric Error) Input Summary IGNNE, in conjunction with the numeric error (NE) bit in CR0, is used by the system logic to control the effect of an unmasked floating-point exception on a previous floating-point instruc- tion during the execution of a floating-point instruction or the WAIT instruction—hereafter referred to as the target instruc-...
Page 196 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 If an unmasked floating-point exception is pending and the tar- get instruction is considered error-insensitive, then the proces- sor ignores the floating-point exception and continues with the execution of the target instruction. FERR is not affected by the state of the NE bit or IGNNE.
Page 197: Init (Initialization)
INIT is not. If INIT and NMI are both asserted during the Stop Grant state (not necessarily simultaneously), the AMD-K5 processor recognizes the INIT after leaving the Stop Grant state, then it recognizes the NMI prior to fetching any instructions.
Page 198 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 writes to a port (such as port 64h in the keyboard controller) that asserts INIT. INIT is also used to support 286 software that must return to Real mode after accessing extended memory in Protected mode.
Page 199 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 asserted three clocks before the BRDY of that write in order to prevent another cycle from starting. INIT invokes the processor’s built-in self test (BIST) if asserted at the falling edge of RESET. The BIST runs a series of tests on the internal hardware that exercise the following resources—...
Page 200: Intr (Maskable Interrupt)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.32 INTR (Maskable Interrupt) Input Summary The assertion of INTR, if enabled by software (unmasked), causes the processor to acknowledge the interrupt and enter an interrupt service routine. The routine is specified by the vector obtained during the acknowledgment.
Page 201: Table 5-13. Interrupt Acknowledge Operation Definition
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 2. Acknowledge—Drives an Interrupt acknowledge operation (a cycle pair) on the bus. System logic must return a BRDY in response to both cycles. Table 5-13 shows the signal val- ues driven during the first and second bus cycles. Both bus cycles are reads, but any data returned on the first cycle is ignored.
Page 202 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The interrupt service routine, upon entry, may re-enable inter- rupts by setting the IF bit in the EFLAGS before servicing the interrupt. This is typically done if the routine is lengthy, so that the processor can respond to higher-priority interrupts while the current interrupt is being serviced, thus allowing nested interrupts.
Page 203 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 INTR is not recognized if asserted while AHOLD, BOFF, or HLDA is asserted, because the processor cannot drive the interrupt acknowledge operation and therefore cannot obtain the interrupt vector. Signal Descriptions 5-87...
Page 204: Inv (Invalidate Cache Line)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.33 INV (Invalidate Cache Line) Input Summary During an inquire cycle, the state of INV determines whether the addressed cache line, if found in the processor’s instruction or data cache, transitions to the invalid or shared state.
Page 205: Ken (External Cache Enable)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.34 KEN (External Cache Enable) Input Summary System logic overrides the cacheability of read cycles with KEN. If KEN is negated during a read cycle, the data returned to the processor will not be cached. If KEN is asserted at that...
Page 206 On the 486 processor, KEN is sampled twice (on the first and last transfer of a burst) and must be asserted at both times for a burst read to be treated as a cache-line fill. On the AMD-K5 and Pentium processors, however, KEN is sampled only on the first clock of a transfer, during BRDY or NA, whichever is first.
Page 207: Lock (Bus Lock)
1, (2) if the bit is cleared to 0, the processor then drives a locked read-modify-write to set the bit to 1. During updates to the Accessed and Busy bits, the AMD-K5 processor drives a locked four-byte read and four- Signal Descriptions 5-91...
Page 208 Thus, up to four bus cycles can occur for misaligned accesses. (The AMD-K5 processor runs certain misaligned bus cycles in the opposite order from the Pentium processor; see the description of SCYC on page 5-114 for details.)
Page 209 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The processor always negates LOCK for at least one idle clock between sequential locked operations. For example, if a read- modify-write is followed by another read-modify-write, there is an unlocked idle clock (sometimes called a dead clock) between the two sequences to allow system logic to reallocate the bus to another bus master.
Page 210 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 writeback is pending when BOFF is negated, the writeback takes precedence over the restarting of the aborted cycles in the locked operation. For purposes of interrupts and exceptions, locked operations are treated by the processor as if the entire multi-cycle opera- tion were a single instruction.
Page 211: M/Io (Memory Or I/O)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.36 M/IO (Memory or I/O) Output Summary The processor drives M/IO to indicate whether it is accessing memory or I/O on the bus. The signal is driven at the same time as the other two cycle definition signals, D/C and W/R. A spe- cific encoding of D/C, M/IO, and W/R identifies one of several special bus cycles.
Page 212: Na (Next Address)
Details NA is an input that is asserted when external memory is pre- pared to accept a pipelined cycle. The AMD-K5 processor drives the pending ADS two clocks after NA is sampled active. NA does not generate pipelined cycles when LOCK is asserted, during writeback cycles, or when there are no pending internal cycles.
Page 213: Nmi (Non-Maskable Interrupt)
INIT, or PRDY is asserted. If INIT and NMI are both asserted during the Stop Grant state (not necessarily simultaneously), the AMD-K5 processor recog- nizes the INIT after leaving the Stop Grant state, then it recog- nizes the NMI prior to fetching any instructions. Current implementations of the Pentium processor do not recognize the NMI in such cases, although future implementations may.
Page 214 NMI interrupt before executing the first instruction of the INTR handler. By contrast, the AMD-K5 processor recog- nizes a pending NMI interrupt after returning (via the IRET instruction) from a prior interrupt.
Page 215: Pcd (Page Cache Disable)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.39 PCD (Page Cache Disable) Output Summary The processor drives PCD to indicate the operating system’s specification of cacheability for the entire current page. Sys- tem logic can use PCD to control external caching.
Page 216 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 In Real mode, or in Protected and Virtual-8086 modes while paging is disabled (PG bit in CR0 cleared to 0): PCD output = CD bit in CR0 (Thus, whenever the CD bit in CR0 is set to 1, the PCD out- put is asserted and the access is non-cacheable.)
Page 217: Pchk (Parity Status)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.40 PCHK (Parity Status) Output Summary The processor asserts PCHK during reads if it detects an even parity error on one or more bytes of D63–D0 during a read cycle. Driven The processor drives PCHK for one clock, two clocks after each BRDY during read cycles.
Page 218: Pen (Parity Enable)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.41 PEN (Parity Enable) Input Summary System logic can assert PEN to enable cycle information latch- ing and (optionally) machine check exception generation for data bus parity errors during read cycles. Sampled The processor samples PEN every BRDY during read cycles.
Page 219: Prdy (Probe Ready)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.42 PRDY (Probe Ready) Output Summary The processor asserts PRDY to acknowledge the system logic’s assertion of R/S or execution of the Test Access Port (TAP) instruction, USEHDT, and to indicate the processor’s entry into the Hardware Debug Tool (HDT) mode for debugging.
Page 220 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Documentation on the HDT is available under nondisclosure agreement to test and debug developers. For information, con- tact your AMD sales representative or field application engi- neer. 5-104 Bus Interface...
Page 221: Table 5-14. Pwt, Writeback/Writethrough, And Mesi
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.43 PWT (Page Writethrough) Output Summary The processor drives PWT to indicate the operating system’s specification of writeback or writethrough state for the entire current page. PWT, together with WB/WT, specifies the data- cache MESI state of cacheable read misses and write hits.
Page 222 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 the accessed line is cached in, transitions to, or remains in the shared state after the access. If PWT is Low and WB/WT is High, the accessed line is cached in, transitions to, or remains in the exclusive state after a read miss or the first write hit.
Page 223: R/S (Run Or Stop)
Hardware Debug Tool (HDT) mode, which supports access to the processor’s DR7–DR0 debug registers through an external debug port. The AMD-K5 processor imple- ments the HDT in a manner different than the Pentium proces- sor’s Probe mode.
Page 224 For information, con- tact your AMD sales representative or field application engi- neer. The AMD-K5 processor implements the HDT mode in a manner different than the Pentium processor’s Probe mode. For details on the processor’s PRDY acknowledgment to R/S, see page 5- 103.
Page 225: Reset (Reset)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.45 RESET (Reset) Input Summary The assertion of RESET initializes the processor to the power- up state. Sampled The processor samples RESET every clock and recognizes it at the next instruction boundary. The RESET process begins at the falling edge of RESET.
Page 226: Table 5-15. Register State After Reset Or Init
FFFF_FFF0h, the same entry point used after INIT, where it expects to find the BIOS entry point. The contents of AMD-K5 processor registers at the conclusion of RESET or INIT is identical to that of the Pentium processor, except that the CPU ID in EDX is 0000_050xh. The upper byte of DX (DH) contains 05h and the lower byte of DX (DL) con- tains 0xh, the processor’s type and stepping identifier.
Page 227 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-15. Register State After RESET or INIT (continued) Contents (hex) Register 0000_050x 0000_0000 0000_0000 0000_0000 0000_0000 FPU Stack R7–R0 0000_0000_0000_0000_0000 FPU Exception Pointer 0_0000_0000_0000 F000 0000 0000 0000 0000 0000 GDTR base:0000_0000 limit:0000...
Page 228: Table 5-16. Outputs At Reset
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-16. Outputs at RESET Output RESET State A31–A3 Floating APCHK BE7–BE0 BREQ BRDY BRDYC CACHE D63–D0 Floating DP7–DP0 FERR HITM HLDA LOCK M/IO PCHK PRDY Unlike INIT, RESET reinitializes the processor’s entire state.
Page 229 BF (BF1–BF0), FLUSH, FRCMC, the hold signals (AHOLD, BOFF, HOLD, and HLDA), INIT, and R/S. Unlike the Pentium processor, the AMD-K5 processor does not recognize RESET in the Hardware Debug Tool (HDT) mode. System hardware or software must exit the HDT (by driving R/ S High) before asserting RESET.
Page 230: Scyc (Split Cycle)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.46 SCYC (Split Cycle) Output Summary The processor asserts SCYC during misaligned, locked trans- fers on the D63–D0 data bus. The processor generates addi- tional bus cycles to complete the transfer of misaligned data.
Page 231 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 If memory reads, memory writes, or I/O reads are misaligned, the AMD-K5 processor runs the bus cycles in the opposite order of the Pentium processor. The AMD-K5 processor trans- fers the low-address portion followed by the high-address por- tion instead of the high-address portion followed by the low- address portion.
Page 232: Smi (System Management Interrupt)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.47 SMI (System Management Interrupt) Input Summary The assertion of SMI causes the processor to enter System Management Mode (SMM). In this mode, which can be trans- parent to standard system and application software, an SMM interrupt service routine accesses a memory space separate from main memory.
Page 233 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 that an I/O device has not been accessed for several minutes. The power management logic can then assert SMI, and the SMM service routine can obtain relevant information from the power management logic with which to make power-down deci- sions under program control.
Page 234 Real mode, and the full 4 Gbytes can be accessed without a segment limit violation. Unlike the Pentium processor, the AMD-K5 processor does not recognize A20M in SMM. The processor exits SMM (that is, the SMM service routine) when it executes the RSM instruction.
Page 235 I/O trap restart slot, and return. During a simultaneous SMI I/O trap (for I/O instruction restart) and debug breakpoint trap, the AMD-K5 processor responds to the SMI first and postpones writing the exception-related information to the stack until after the return from SMM via the RSM instruction.
Page 236 NMI interrupt before executing the first instruction of the INTR handler. By contrast, the AMD-K5 processor recog- nizes a pending NMI interrupt after returning (via the IRET instruction) from a prior interrupt.
Page 237: Smiact (System Management Interrupt Active)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.48 SMIACT (System Management Interrupt Active) Output Summary The processor acknowledges the assertion of SMI with the assertion of SMIACT. The acknowledgment signifies the pro- cessor’s readiness to enter System Management Mode (SMM) and begin executing the service routine for that interrupt mode.
Page 238: Stpclk (Stop Clock)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.49 STPCLK (Stop Clock) Input Summary The assertion of STPCLK causes the processor to complete any in-progress bus cycle and enter the Stop Grant state (proces- sor’s internal clock stopped), from which it can subsequently transition to the Stop Clock state (bus clock stopped).
Page 239 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 relevant information and decide to power itself (the processor) down, and the decision would be communicated to the power management logic, which would assert STPCLK to the proces- sor and, optionally, stop driving CLK to the processor and other logic.
Page 240 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 the Halt state, the processor transitions to the Stop Grant state; it then returns to the Halt state when STPCLK is negated. No processor registers are saved before entering the Halt state because the processor returns to the next unexe- cuted instruction in program order when it returns to its prior operating mode.
Page 241 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 mal writeback (immediately if AHOLD is asserted, or delayed if BOFF or HOLD are asserted) and returns to the state from which it entered the Stop Grant Inquire state in the clock in which it negates HITM. If HITM is not asserted, the processor returns two clocks after EADS.
Page 242 STPCLK. The AMD-K5 proces- sor does not guarantee this. In the Halt or Stop Grant states, the AMD-K5 processor can- not enter a low-power state if it does not have the bus (that is, if AHOLD, BOFF or HLDA is asserted). The same may not be true of the Pentium processor.
Page 243: Tck (Test Clock)
Section 7.8 on page 7-19 summarizes the implementation of TAP testing on the AMD-K5 processor. System logic should tie TCK High if TAP testing is not implemented. See the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1) specification for details on how the...
Page 244: Tdi (Test Data Input)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.51 TDI (Test Data Input) Input Summary TDI carries input test data and instructions for testing on the Test Access Port (TAP). Sampled The processor samples TDI every rising TCK edge, but only during the shift_IR and shift_DR states. TDI has an internal pullup resistor.
Page 245: Tdo (Test Data Output)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.52 TDO (Test Data Output) Output Summary TDO carries output data for testing on the Test Access Port (TAP). Driven and Floated The processor drives TDO every falling TCK edge, but only during the shift_IR and shift_DR states. It is floated at all other times.
Page 246: Tms (Test Mode Select)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.53 TMS (Test Mode Select) Input Summary TMS specifies the test function and sequence of test changes for testing on the Test Access Port (TAP). Sampled The processor samples TMS every rising TCK edge. TMS has an internal pullup resistor.
Page 247: Trst (Test Reset)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.54 TRST (Test Reset) Input Summary The assertion of TRST initializes the Test Access Port (TAP) by resetting its state machine. Sampled TRST is an asynchronous input. Unlike other asynchronous inputs, no synchronous setup and hold time are specified for TRST.
Page 248: W/R (Write Or Read)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.55 W/R (Write or Read) Output Summary The processor drives W/R to indicate whether it is performing a write or read cycle on the bus. The signal is driven at the same time as the other two cycle definition signals: D/C and M/IO.
Page 249: Wb/Wt (Writeback Or Writethrough)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.2.56 WB/WT (Writeback or Writethrough) Input Summary WB/WT, together with PWT, specifies the data-cache MESI state of cacheable read misses and write hits. Sampled The processor samples WB/WT in the same clock as the first BRDY of a bus cycle or NA, whichever comes first.
Page 250: Table 5-17. Mesi-State Transitions For Reads
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 the exclusive state, a subsequent write hit to the same line tran- sitions the line to the modified state. During write hits, the states of PWT and WB/WT can only change a line from shared to exclusive;...
Page 251: Table 5-18. Mesi-State Transitions For Writes
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-18. MESI-State Transitions for Writes Result of Cache Lookup Write Hit Signal or Event Write Miss exclusive shared or modified — — — — — CACHE, PCD — — — — — —...
Page 252: Bus Cycle Overview
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Bus Cycle Overview The bus signals described in the previous section combine to form various types of bus transactions, or bus cycles. This sec- tion summarizes the general features of the bus cycles: cycle definition, addressing, alignment, and priorities.
Page 253: Addressing
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 the signals shown in Table 5-23 on page 5-180. In addition to the processor-driven bus cycles shown in Table 5-19, system logic can drive inquire cycles to the processor. These bus cycles are described later, in Section 5.4.4 on page 5-156.
Page 254 SCYC throughout the misaligned sequence of bus cycles. If memory reads, memory writes, or I/O reads are misaligned, the AMD-K5 processor runs the bus cycles in the opposite order of the Pentium processor. The AMD-K5 processor trans- fers the least-significant bytes first followed by the most-signif- icant bytes.
Page 255: Bus Speed And Typical Dram Timing
DRAM-page hit and 8-3-3-3 for a DRAM-page miss. 5.3.5 Bus-Cycle Priorities The AMD-K5 processor can support only one on-going bus cycle at a time—pending bus cycles are not buffered. System logic maintains the ultimate control over the bus. The proces- sor asserts BREQ to request control of the bus.
Page 256: Bus Cycle Timing
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Bus Cycle Timing The following sections describe and illustrate the timing and relationship of bus signals during various types of bus cycles. Only a representative set of bus cycles are illustrated. Many more combinations are possible.
Page 257: Single-Transfer Reads And Writes
8 bytes. Misaligned instructions or operands result in a split cycle, which requires multiple transactions on the bus. During single-transfer (non-cacheable) code fetches, the AMD-K5 and Pentium processors read 8 bytes, not 16 bytes as the 486 pro- cessor does.
Page 258 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 BRDY, the processor latches the physical address and cycle definition of the failed bus cycle in its 64-bit machine-check address register (MCAR) and its 64-bit machine-check type register (MCTR). For details on such parity errors, see the descriptions of PCHK and PEN on pages 5-101 and 5-102.
Page 259: Figure 5-2. Single-Transfer Memory Read And Write
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY BREQ CACHE D63–D0 DP7–DP0 M/IO PCHK WB/WT Read Write Figure 5-2. Single-Transfer Memory Read and Write Bus Cycle Timing 5-143...
Page 260: Single-Transfer Memory Write Delayed By Ewbe Signal
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Single-Transfer Figure 5-3 shows two consecutive memory writes. The first Memory Write write fills an external write buffer and the second write is Delayed by EWBE stalled for three clocks by the negation of EWBE.
Page 261: Figure 5-3. Single-Transfer Memory Write Delayed By Ewbe Signal
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY D63–D0 EWBE M/IO Effective Write Write BRDY Figure 5-3. Single-Transfer Memory Write Delayed by EWBE Signal Bus Cycle Timing 5-145...
Page 262: Figure 5-4. I/O Read And Write
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 I/O Read and Write Figure 5-4 shows an I/O read followed by an I/O write. The pro- cessor accesses I/O when it executes an I/O instruction (any of the INx or OUTx instructions). Accesses to memory-mapped I/O ports appear on the bus as accesses to memory rather than to the I/O address space.
Page 263: Table 5-20. Bus-Cycle Order During Misaligned Transfers
The processor writes the word to I/O address 90h, followed by the word to I/O address 8Eh. The AMD-K5 processor performs misaligned memory read, memory write, and I/O read transfers in the reverse order of the Pentium processor, but misaligned I/O write transfers are performed in the same order on both processors.
Page 264: Figure 5-5. Single-Transfer Misaligned Memory And
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY D63–D0 M/IO SCYC Read Read Write Write Figure 5-5. Single-Transfer Misaligned Memory and I/O Transfers 5-148 Bus Interface...
Page 265: Burst Cycles
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.4.3 Burst Cycles The processor drives burst cycles, which consist of four sequen- tial eight-byte (quadword) transfers on the data bus, only in the following cases: Burst Read—Cache-line fills from memory. These burst reads occur when the processor asserts CACHE during ADS and system logic asserts KEN during the first BRDY of a read cycle.
Page 266: Table 5-21. Address-Generation Sequence During Bursts
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 5-21. Address-Generation Sequence During Bursts Address Driven By Addresses of Subsequent Quadwords Processor on A31–A3 Generated By System Logic Quadword 1 Quadword 2 Quadword 3 Quadword 4 ...00h ...08h ...10h ...18h ...08h ...00h ...18h...
Page 267: Figure 5-6. Burst Reads
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 (rather than BRDY) is asserted. KEN and WB/WT are validated by either NA or BRDY, whichever comes first. NA will not gen- erate a pipelined cycle in the event that there are no pending internal cycles.
Page 268: Figure 5-7. Burst Read (Na Sampled)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 M/IO WB/WT Read Read Figure 5-7. Burst Read (NA Sampled) 5-152 Bus Interface...
Page 269: Burst Writeback
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Burst Writeback Figure 5-8 shows a burst read followed by a writeback. Write- backs are the only type of burst write that the processor per- forms. They can be initiated by the processor or by system...
Page 270 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 (BE7–BE0 = 00h). Thus, A4–A3 are always 0 for writebacks. During inquire cycle writebacks, the processor does the same thing, except that if system logic holds AHOLD asserted throughout the writeback, the processor lets system logic pro- vide the address.
Page 271: Figure 5-8. Burst Writeback Due To Cache-Line Replacement
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 EADS M/IO WB/WT Read Write Figure 5-8. Burst Writeback Due To Cache-Line Replacement Bus Cycle Timing 5-155...
Page 272: Bus Arbitration And Inquire Cycles
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.4.4 Bus Arbitration and Inquire Cycles The processor bus may be required by another bus master, which may need to drive its own cycles on the bus, or by system logic, which may need to drive an inquire cycle to the proces- sor or resolve bus deadlock.
Page 273: Ahold-Initiated Inquire Miss
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 2. Two clocks after the assertion of BOFF or AHOLD, or one clock after sampling HLDA asserted when HOLD is used, assert EADS while driving a cache-line address on A31–A5, and assert or negate INV. The processor latches the address when it samples EADS asserted.
Page 274: Figure 5-9. Ahold-Initiated Inquire Miss
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 For an AHOLD inquire cycle to be recognized, AHOLD must have been asserted continuously for two clocks at the time EADS is asserted. AHOLD and BOFF can be asserted in con- junction with each other without interfering with EADS recog- nition, as long as the sampling criteria for at least one of the signals (AHOLD or BOFF) is met.
Page 275: Figure 5-10. Ahold-Initiated Inquire Hit To Shared Or Exclusive Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 AHOLD-Initiated Figure 5-10 shows an example similar to Figure 5-9, minus the Inquire Hit to Shared address parity error, but this inquire cycle hits either a shared or Exclusive Line or exclusive line in the cache, as indicated by the assertion of HIT and the negation of HITM two clocks after the assertion of EADS.
Page 276: Ahold-Initiated Inquire Hit To Modified Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 AHOLD-Initiated Figure 5-11 shows the same sequence as in Figure 5-10, but this Inquire Hit to time the inquire cycle hits a modified line. As in Figure 5-10, Modified Line system logic asserts INV with EADS. Two clocks later, the pro- cessor asserts both HIT and HITM.
Page 277: Figure 5-11. Ahold-Initiated Inquire Hit To Modified Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 AHOLD BE7–BE0 BRDY D63–D0 EADS HITM M/IO Read Inquire Writeback Figure 5-11. AHOLD-Initiated Inquire Hit to Modified Line Bus Cycle Timing 5-161...
Page 278: Bus Backoff (Boff)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Bus Backoff (BOFF) BOFF provides the fastest response of the three bus-hold inputs. Unlike AHOLD and HOLD, BOFF does not permit an in-progress bus cycle to complete. It forces the processor off the bus in the next clock, aborting any in-progress bus cycle that the processor may have begun.
Page 279: Figure 5-12. Basic Boff Operation
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BOFF BRDY D63–D0 M/IO Read Cycle by Restarted (Aborted) Another Master Read Figure 5-12. Basic BOFF Operation Bus Cycle Timing 5-163...
Page 280: Boff-Initiated Inquire Hit To Modified Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 BOFF-Initiated Figure 5-13 shows a burst read interrupted by the assertion of Inquire Hit to BOFF for the purpose of an inquire cycle. One clock after sam- Modified Line pling BOFF asserted, the processor aborts the burst read and floats its bus.
Page 281: Figure 5-13. Boff-Initiated Inquire Hit To Modified Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BOFF BRDY CACHE D63–D0 EADS HITM M/IO Read Restarted Inquire Writeback (aborted) Read Figure 5-13. BOFF-Initiated Inquire Hit to Modified Line Bus Cycle Timing 5-165...
Page 282: Hold-Initiated Inquire Hit To Shared Or Exclusive Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 HOLD-Initiated Figure 5-14 shows HOLD asserted in the same clock that the Inquire Hit to Shared processor begins a read cycle. The processor completes the or Exclusive Line read (which is a burst read) and asserts HLDA two clocks after the last BRDY of the in-progress cycle.
Page 283: Figure 5-14. Hold-Initiated Inquire Hit To Shared Or Exclusive Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 EADS HITM HLDA HOLD M/IO Read Inquire Figure 5-14. HOLD-Initiated Inquire Hit to Shared or Exclusive Line Bus Cycle Timing 5-167...
Page 284: Figure 5-15. Hold-Initiated Inquire Hit To Modified Line
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 HOLD-Initiated Figure 5-15 shows an example similar to the one in Figure 5-14, Inquire Hit to except that the inquire cycle hits a modified line (both HIT and Modified Line HITM asserted two clocks after EADS). System logic negates HOLD in the clock after EADS, and two clocks later (one clock after HIT and HITM transition) the processor negates HLDA.
Page 285: Locked Cycles
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.4.5 Locked Cycles The processor asserts LOCK across certain sequences of mem- ory bus cycles that require integrity. These include interrupt acknowledge operations, descriptor-table updates, page-direc- tory and page-table updates, and exchange operations. In addi- tion, the processor asserts LOCK during bus cycles initiated by any instruction that has the LOCK prefix.
Page 286: Figure 5-16. Basic Locked Operation
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 LOCK M/IO Read Write Read Write Figure 5-16. Basic Locked Operation 5-170 Bus Interface...
Page 287: Tlb Miss (4-Kbyte Page)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 TLB Miss Figure 5-17 shows a TLB miss for a 4-Kbyte page. An overview (4-Kbyte Page) of the 4-Kbyte paging mechanism is illustrated in Figure 3-2 on page 3-5. The paging mechanism for 4-Mbyte pages (Figure 3-3 on page 3-6) is similar but somewhat simpler.
Page 288: Figure 5-17. Tlb Miss (4-Kbyte Page)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 EADS LOCK M/IO Read that caused Read PDE Read PTE Read PTE Write PTE TLB miss Figure 5-17. TLB Miss (4-Kbyte Page) 5-172 Bus Interface...
Page 289: Locked Operation With Boff Intervention
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Locked Operation Unlike AHOLD and HOLD, BOFF does not permit an in- with BOFF progress bus cycle to complete. It forces the processor off the Intervention bus in the next clock, aborting any in-progress bus cycle that the processor may have begun.
Page 290: Figure 5-18. Locked Operation With Boff Intervention
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BOFF BRDY CACHE D63–D0 LOCK M/IO Read Aborted Write Restarted Write Figure 5-18. Locked Operation with BOFF Intervention 5-174 Bus Interface...
Page 291: Table 5-22. Interrupt Acknowledge Operation Definition
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Interrupt Figure 5-19A shows system logic asserting INTR during a burst Acknowledge read. The figure shows the resulting bus behavior, up to the Operation start of the interrupt handler. When the processor recognizes an INTR interrupt at the next instruction-retirement bound- ary, the processor performs the following actions: Finish In-Progress Bus Cycle—In Figure 5-19A, a burst read is...
Page 292 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 the processor executes housekeeping microcode, the processor prepares to service the interrupt by performing the following accesses on the bus: IDT Lookup—Using the interrupt vector and, in Protected mode, the base address of the interrupt descriptor table...
Page 293 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 EADS INTR LOCK M/IO Interrupt INTR Asserted Acknowledge Cycles Figure 5-19A. Interrupt Acknowledge Operation Part 1 Bus Cycle Timing 5-177...
Page 294 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 EADS INTR LOCK M/IO IDT Lookup GDT Lookup Figure 5-19B. Interrupt Acknowledge Operation Part 2 5-178 Bus Interface...
Page 295 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 EADS INTR LOCK M/IO Code fetch Write for interrupt to stack Figure 5-19C. Interrupt Acknowledge Operation Part 3 Bus Cycle Timing 5-179...
Page 296: Table 5-23. Encodings For Special Bus Cycles
1. For all special bus cycles, D/C = 0, M/IO = 0 and W/R = 1. System logic must return BRDY in response to this cycle. 2. The message in a branch-trace message special bus cycle is different in the AMD-K5 and Pentium processors.
Page 297: Figure 5-20. Basic Special Bus Cycle (Halt Cycle)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Basic Special Bus Figure 5-20 shows a basic special bus cycle, which is defined Cycle during ADS by D/C = 0, M/IO = 0, and W/R = 1 and differenti- ated by BE7–BE0 and A31–A3. In this example, BE7–BE0 = FBh and A31–A3 = 0, so it is the special cycle the processor...
Page 298: Figure 5-21. Shutdown Cycle
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Shutdown Cycle Figure 5-21 shows a shutdown and the special cycle that fol- lows. The processor enters shutdown when an interrupt or exception occurs during the handling of a double fault (vector 8), which amounts to a triple fault. When the processor encoun- ters such a triple fault, it stops its activity on the bus and gen- erates the special bus cycle for shutdown (BE7–BE0 = FEh).
Page 299: Figure 5-22. Flush-Acknowledge Cycle
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 FLUSH-Acknowledge Figure 5-22 shows the FLUSH-acknowledge special bus cycle, Cycle which the processor drives in response to system logic’s asser- tion of FLUSH. This example shows the processor completing other unrelated bus cycles following the assertion of FLUSH.
Page 300: Figure 5-23. Cache-Invalidation Cycle (Invd Instruction)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Cache-Invalidation Figure 5-23 shows the cache-invalidation special bus cycle, Cycle (INVD which the processor drives in response to the execution of the Instruction) INVD instruction. The INVD instruction causes the processor to invalidate each line in its instruction and data caches. Modi- fied lines in the data cache are not written back.
Page 301: Figure 5-24A. Cache-Writeback And Invalidation Cycle
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Cache-Writeback Figure 5-24A and Figure 5-24B show the cache-writeback and and Invalidation invalidation special bus cycle, followed by the cache-invalida- Cycle (WBINVD tion special bus cycle. The processor drives these two special Instruction) cycles after executing the WBINVD instruction.
Page 302: Figure 5-24B. Cache-Writeback And Invalidation Cycle
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 LOCK M/IO Cache invalidation Cache Writeback and special cycle invalidation special cycle Figure 5-24B. Cache-Writeback and Invalidation Cycle (WBINVD Instruction) Part 2 5-186 Bus Interface...
Page 303: Table 5-24. Branch-Trace Message Special Bus Cycle Fields
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Branch-Trace Figure 5-25 shows the two branch-trace message special bus Message Cycles cycles that the processor generates for each taken branch when branch tracing is enabled as described in Section 7.6 on page 7-17. System logic can accumulate the address and data bus values for debugging or profiling.
Page 304: Figure 5-25. Branch-Trace Message Cycle
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 M/IO Branch-trace Message special cycles Figure 5-25. Branch-Trace Message Cycle 5-188 Bus Interface...
Page 305: Mode Transitions, Reset, And Testing
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 5.4.7 Mode Transitions, Reset, and Testing System logic can control the system-management, clocking, and initialization states of the processor with SMI, STPCLK, INIT, and RESET. The following examples shows the proces- sor’s response to some of the signals.
Page 306 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 FLUSH LOCK M/IO SMIACT SMIACT SMI Asserted Asserted Figure 5-26A. Transition from Normal Execution to SMM Part 1 5-190 Bus Interface...
Page 307 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 FLUSH LOCK M/IO SMIACT Begin save of processor state Figure 5-26B. Transition from Normal Execution to SMM Part 2 Bus Cycle Timing 5-191...
Page 308: Stop-Grant And Stop-Clock States
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Stop-Grant and Stop- Figure 5-27A and Figure 5-27B show the processor’s transition Clock States from normal execution to the Stop-Grant state, then to the Stop-Clock state, and finally back to normal execution. The series of transitions begins when system logic asserts STPCLK.
Page 309 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 LOCK M/IO STPCLK Stop Clock State Stop Grant STPCLK Special Cycle Asserted Figure 5-27A. Stop-Grant and Stop-Clock Modes Part 1 Bus Cycle Timing 5-193...
Page 310 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE D63–D0 LOCK M/IO STPCLK Normal State Figure 5-27B. Stop-Grant and Stop-Clock Modes Part 2 5-194 Bus Interface...
Page 311: Mode To Real Mode
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 INIT-Initiated Figure 5-28 shows an example in which the operating system Transition from writes to an I/O port, causing system logic to assert INIT. The Protected Mode to assertion of INIT starts an extended microcode sequence that Real Mode terminates with a code fetch from the Reset location.
Page 312: Figure 5-28. Init-Initiated Transition From Protected Mode To Real Mode
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A31–A3 BE7–BE0 BRDY CACHE … D63–D0 INIT M/IO RESET Code fetch INIT Asserted from FFFF_FFF0h Figure 5-28. INIT-Initiated Transition from Protected Mode to Real Mode 5-196 Bus Interface...
Page 313: System Design
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 System Design This chapter summarizes topics that may be of help to system board designers. The discussions touch on the design of mem- ory, cache, System Management Mode (SMM), clock control (power management), and a few other topics. Many of the details that relate to this subject are also covered in Chapter 5, which describes the processor’s signals and bus cycles not only...
Page 314: Memory Map
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.1.1 Memory Map Figure 6-1 shows a typical physical memory map for a DOS- based desktop system after DOS boots. Various regions of this memory map to RAM or ROM on the motherboard and adapter boards.
Page 315: Figure 6-1. Typical Desktop-System Bios Memory Map
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 FFFF_FFFF 4 Gbyte Boot ROM FFFF_C000 Extended Hardware (expanded) Alias Memory 000F_FFFF 1 Mbyte Aliased Boot ROM 000F_C000 High BIOS ROM Memory Device ROM Memory-Mapped I/O BIOS Remap 0009_FFFF 640 Kbyte During Boot (conventional)
Page 316: Memory-Decoder Aliasing Of Boot Rom Space
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.1.2 Memory-Decoder Aliasing of Boot ROM Space The processor boots in Real mode at address FFFF_FFF0h. However, because the boot ROM space must be accessed after the first far jump in the processor’s Real mode, which gener-...
Page 317: Smm Memory Space And Cacheability
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 entries because these data structures are cached only in CR3 and the TLBs. System logic normally defines the cacheable address space by implementing external registers which BIOS or other system software initializes during boot with the cacheable (or non- cacheable) ranges of the address space.
Page 318 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 During boot, the address decoder must allow BIOS to address the SMM memory area in the main memory address space without entering into the SMM mode in order to initialize it with configuration parameters and the SMM service routine.
Page 319: Figure 6-2. Default Smm Memory Map
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Fill Down 0003_FFFF State-Save Area 0003_FE00 32-Kbyte Minimum Service Routine Service Routine Entry Point 0003_8000 SMM Base Address (CS) 0003_0000 Figure 6-2. Default SMM Memory Map System logic controls the cacheability of SMM memory with KEN in the same way that it controls the cacheability of mem- ory space.
Page 320: Cache
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The cacheability of SMM memory has both advantages and dis- advantages. By caching SMM memory, the advantage of faster repetitive accesses is offset by delays due to overwriting cache lines that may otherwise be reusable after returning from SMM.
Page 321: L2 Cache
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 page table entries to control caching properties for specific physical pages. The PCD and PWT bits control the state of the PCD and PWT output signals, which system logic can use to control L2 caching.
Page 322: Writethrough Vs. Writeback Coherency States
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 writethroughs, which are driven as single writes rather than burst writes. From the system’s viewpoint, the cacheability of bus cycles is controlled by the KEN and WB/WT inputs, as described in Sec- tion 6.1.3 on page 6-4. During reads, system logic can use the assertion of CACHE to initiate a table lookup of cacheable addresses.
Page 323 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A memory write that occurs after a previous cache up- • date to the same location is a writeback. Writebacks are driven as burst cycles on the bus. Coherency State—There is a relationship between MESI...
Page 324: Inquire Cycles
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Repetitive writes to the same location are slower than in • writeback mode. No updates to the data cache are hidden from the sys- • tem. When returning from SMM with SMM memory cache- •...
Page 325 If INV was negated with EADS, a hit leaves the line in the shared state, or transitions it from the modified to shared state. On the AMD-K5 processor, the maximum inquire or invalida- tion rate with inquire cycles is one every two clocks, because HIT and HITM change state two clocks after EADS, and EADS can be asserted in the same clock in which HITM is negated.
Page 326: Bus Arbitration For Inquire Cycles
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Inquire cycle logic in systems with look-aside caches can be simplified by monitoring only HITM and ignoring HIT. This works because the resulting state of a hit line is determined only by the state of INV during the inquire as follows: If INV is negated during a hit, the hit line—whether shared,...
Page 327: Boff Arbitration
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 cycles is of paramount importance. Support for BOFF is usu- ally needed to resolve potential deadlock problems that arise as a result of inquire cycles, and if BOFF is supported, there is usually no reason to support HOLD. The sections that follow further describe these relative advantages and disadvantages.
Page 328: Figure 6-3. Boff Example
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 3. The processor responds with HITM to system logic. 4. System logic asserts BOFF to the requesting master. (HITM from the processor can be used to generate BOFF.) 5. The other master negates BOFF to the processor so that the processor can write back its modified line to main memory and the shared L2 cache.
Page 329: Ahold Arbitration
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 AHOLD Arbitration AHOLD’s sole function is to support inquire cycles. The asser- tion of AHOLD by system logic only gets control of the address bus, leaving the data bus available to the processor for the completion of an in-progress bus cycle.
Page 330: Figure 6-4. Ahold And Boff Example
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Writeback AMD-K5 Processor HITM AHOLD EADS Look-Through L2 Cache HITM 4 BOFF EADS System Logic Memory Access System Bus BOFF Other Main Memory Master Figure 6-4. AHOLD and BOFF Example 6-18 System Design...
Page 331: Hold Arbitration
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 HOLD Arbitration System logic can use the HOLD (request) and HLDA (acknowl- edge) protocol to gain control of the address and data buses. Like BOFF, HOLD/HLDA gains control of both the address and data buses but only after the processor completes any in- progress bus cycle or a sequence of cycles, like a locked cycle.
Page 332 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The writethrough to memory must be accompanied by an invalidation of this line in any other caching master’s cache. 3. During the second write to that line, the processor updates its shared line and writes through to the exclusive line of the L2 cache.
Page 333: Figure 6-5. Write-Once Protocol
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 WB/WT = 0 Line Fill Writethrough WB/WT = 0 AMD-K5 Processor Writethrough WB/WT = 1 WB/WT = 0 Look-Through WB/WT = 1 L2 Cache System Logic System Bus Other Main Memory Master Figure 6-5. Write-Once Protocol...
Page 334: Cache Invalidations
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.2.7 Cache Invalidations The term invalidation usually means one of the following things: Individual Cache Lines—Writebacks and/or invalidations of single lines in the instruction and data caches can be done with inquire cycles (driven by system logic) or internal snoops (initiated by the processor).
Page 335: System Management Mode (Smm)
AMD-K5 and Pentium processors of masking linear vs. physical addresses is not visible to software because linear and physical addresses are identical in Real mode, and the AMD-K5 proces- sor samples A20M only in Real mode. System Management Mode (SMM) SMM is an operating mode entered via an interrupt and per- formed by an interrupt service routine.
Page 336: Operating Mode And Default Register Values
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.3.1 Operating Mode and Default Register Values The software environment in SMM has the following features: Addressing as in Real mode 4-Gbyte segment limit Default 16-bit operand, address, and stack size, although instruction prefixes can override these defaults...
Page 337: Table 6-1. Initial State Of Registers In Smm
SMM base address. The SMM service routine can alter any of the read/write values in the state-save area. The con- tents of any reserved locations in the state-save area are not necessarily the same between the AMD-K5 processor and the Pentium or 486 processors. System Management Mode (SMM)
Page 338: Table 6-2. Smm State-Save Area Map
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 6-2. SMM State-Save Area Map Offset (hex) Contents Size (bits) Type read-only FFFC FFF8 read-only FFF4 EFLAGS read/write read/write FFF0 read/write FFEC FFE8 read/write read/write FFE4 read/write FFE0 FFDC read/write FFD8 read/write read/write...
Page 339 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 6-2. SMM State-Save Area Map (continued) Offset (hex) Contents Size (bits) Type FF80 TR Attributes 12 (upper 20 reserved) read-only FF7C TR Base read-only TR Limit 20 (upper 12 reserved) read-only FF78 FF74...
Page 340: Smm Revision Identifier
These fields are the same as in the Pentium processor. Unlike the Pentium processor, however, the I/O trap restart and the SMM base address relocation functions are always enabled in the AMD-K5 processor and do not need to be specifically enabled. 6.3.4...
Page 341 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 If the SMM base address is rewritten, the processor saves its state at the new base address the next time SMM is entered, and each time thereafter, until RESET. The relocated addresses for the SMM memory will then be as follows: SMM base address—Default: 0003_0000h.
Page 342: Halt Restart Slot
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.3.5 Halt Restart Slot During entry into SMM, the halt restart slot at offset FF02h in the SMM state-save area specifies if SMM was entered from the Halt state. Before returning from SMM, the halt restart slot...
Page 343: I/O Trap Dword
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.3.6 I/O Trap Dword If the assertion of SMI is recognized on the boundary of an I/O instruction, the I/O trap dword at offset FFA4h in the SMM state-save area contains information about the instruction. The fields of the I/O trap dword are configured as follows: Bits 31–16—I/O port address...
Page 344: Exceptions And Interrupts In Smm
I/O restart slot (offset FF00) to 00FFh During a simultaneous SMI I/O-instruction trap and debug breakpoint trap, the AMD-K5 processor first responds to the SMI and postpones writing the exception-related information to the stack until after the return from SMM via the RSM instruction.
Page 345: Smm Compatibility With Pentium Processor
NMI interrupt before executing the first instruction of the INTR handler. By contrast, the AMD-K5 processor recog- nizes a pending NMI interrupt after returning (via the IRET instruction) from a prior interrupt.
Page 346: State Transitions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 tions can be entered from any of the processor’s normal operat- ing modes (Real, Virtual-8086, or Protected mode), from system management mode (SMM), or from the Halt state. In typical PC systems that implement power control, the STP-...
Page 347 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 state, and it returns to the Halt state when STPCLK is negated. No processor registers are saved before entering the Halt state because the processor returns to the next unexecuted instruc- tion in program order when it returns to its prior operating mode.
Page 348: Figure 6-6. Clock Control State Transitions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 STPCLK Asserted HLT Instruction Normal Mode - Real STPCLK Negated, RESET, SMI, INIT, - Virtual-8086 or RESET Asserted or INTR Asserted - Protected - SMM STPCLK Asserted STPCLK Negated EADS EADS Stop Grant Halt...
Page 349: Stop Grant State
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6.4.3 Stop Grant State The assertion of STPCLK causes the processor to enter the Stop Grant state. The processor can enter the Stop Grant state from the normal operating modes (Real, Protected, or Virtual- 8086), SMM, or the Halt state.
Page 350: Stop Clock State
6.4.6 Clock Control Compatibility with Pentium Processor The differences in clock control functions between the AMD-K5 and Pentium processors are described in Section A.5 on page A-12. Power and Ground Design All of the processor input signals operate at 3 V except CLK, which can operate at 3 V or 5 V.
Page 351 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 immediately after AHOLD is negated. If the processor is also driving data with BRDY on the data bus at the same time, the processor then drives 96 bits simultaneously and ground- bounce spikes can occur. Such ground-bounce spikes can be...
Page 352: Figure 6-7. V
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Power-Up Requirements During power-up, CLK should be toggling and RESET should be asserted as V is ramping toward normal operating volt- age. Figure 6-7 shows this timing. After V and CLK reach specification, RESET must be asserted for a minimum of 1 ms to allow the phase-lock loop to synchronize.
Page 353: Noise Reduction
Use at least three vias to the +3-V processor power plane • for the output power connection. AMD recommends using a split power plane to isolate the pro- cessor from the rest of the motherboard. This approach Noise Reduction 6-41...
Page 354: Thermal Design
Such cooling products are widely available. For detailed speci- fications and assistance is selecting a product, contact your AMD field application engineer or browse the AMD home page on the World Wide Web (see Section 6.9 for details). When gluing a heat sink to the processor case, follow these guidelines: Use thermal paste.
Page 355: Design Support And Peripheral Products
AMD-K5 processor. You can locate the FAE nearest you by contacting one of the AMD offices listed in this manual. You can also find support information on AMD’s World Wide Web pages.
Page 356 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 6-44 System Design...
Page 357: Test And Debug
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Test and Debug The AMD-K5 processor has the following modes in which pro- cessor and system operation can be tested or debugged: Hardware Configuration Register (HWCR)—The HWCR is a model-specific register that contains configuration bits that enable cache, branch tracing, debug, and clock control func- tions.
Page 358 R/S Low or loads the AMD-K5 processor’s Test Access Port (TAP) instruction register with the USEHDT instruction. The test-related signals and their descriptions include the fol- lowing: FLUSH—Page 5-65...
Page 359: Hardware Configuration Register (Hwcr)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Hardware Configuration Register (HWCR) The Hardware Configuration Register (HWCR) is a model-spe- cific register (MSR) that contains configuration bits that enable cache, branch tracing, debug, and clock control func- tions. The WRMSR and RDMSR instructions access the HWCR when the ECX register contains the value 83h, as described in Section 3.3.5 on page 3-33.
Page 360: Table 7-1. Hardware Configuration Register (Hwcr) Fields
Disables stopping of internal processor clocks in the Disable Stopping Halt and Stop Grant states. DSPC Processor Clocks 0 = enabled, 1 = disabled. Notes: Documentation on the Hardware Debug Tool (HDT) is available from AMD under a nondisclosure agreement. Test and Debug...
Page 361: Built-In Self Test (Bist)
The TLB is tested by microcode. Unlike the Pentium processor, the AMD-K5 processor does not report parity errors on IERR for every cache or TLB access. Instead, the AMD-K5 processor fully tests its caches during the BIST. EADS should not be asserted during a BIST.
Page 362: Table 7-2. Bist Error Bit Definition In Eax Register
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 LFSR signature test on the PLA, in that order. Upon comple- tion of the PLA test, the processor transfers the test result from an internal Hardware Debug Test (HDT) data register to the EAX register for external access, resets the internal micro- code, and begins normal code fetching.
Page 363: Output-Float Test
The Output-Float Test mode can only be exited by asserting RESET again. On the AMD-K5 and Pentium processors, FLUSH is an edge- triggered interrupt. On the 486 processor, however, the signal is a level-sensitive input.
Page 364: Figure 7-2. Array Access Register (Aar)
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 4-Kbyte TLB—128-entry, 4-way, set associative • Linear-tag array Page array • 4-Mbyte TLB—4-entry, fully associative Linear-tag array • Page array • 7.4.1 Array Access Register (AAR) The 64-bit Array Access Register (AAR) is a model-specific...
Page 365: Table 7-3. Array Ids In Array Pointers
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 7.4.2 Array Pointer The array pointers entered in EDX (Figures 7-3 through 7-8, top) specify particular array locations. For example, in the data- and instruction-cache arrays, the way (or column) and set (or index) in the array pointer specifies a cache line in the 4- way, set-associative array.
Page 366: Figure 7-3. Test Formats: Data-Cache Tags
7–0 of the array pointer). If the linear tag array (E1h) were accessed, the data read or written includes the tag and the status bits. The details of the valid fields in EAX are shown in Appendix A of the AMD-K5 Processor Software Development Guide, order# 20007. EDX: Array Pointer...
Page 367: Figure 7-4. Test Formats: Data-Cache Data
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 EDX: Array Pointer 31 30 29 28 27 Array ID 0 0 0 0 0 0 0 0 0 Dword (E0h) EAX: Test Data Valid Bits (E0h) Data Figure 7-4. Test Formats: Data-Cache Data...
Page 368: Figure 7-5. Test Formats: Instruction-Cache Tags
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 EDX: Array Pointer 31 30 29 28 27 Array ID 0 0 0 0 0 0 0 0 0 0 0 0 (E5h, EDh, E6h, E7h) EAX: Test Data 0 0 0 0 0 0 0 0 0 0 0 0...
Page 369: Figure 7-6. Test Formats: Instruction-Cache Instructions
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 EDX: Array Pointer 31 30 29 28 27 20 19 Array ID Opcode 0 0 0 0 0 0 0 0 (E4h) Bytes EAX: Test Data 26 25 0 0 0 0 0 0...
Page 370: Figure 7-7. Test Formats: 4-Kbyte Tlb
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 EDX: Array Pointer 31 30 29 28 27 Array ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (E8h, E9h) EAX: Test Data 0 0 0 0 0 0 0 0 0 0...
Page 371: Figure 7-8. Test Formats: 4-Mbyte Tlb
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 EDX: Array Pointer 31 30 29 28 27 Array ID Entry 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EAh, EBh) EAX: Test Data...
Page 372: Debug Registers
DR3–DR0 Entering the bit pattern, 10b, in the corresponding 2-bit R/W field in DR7 All data breakpoints on the AMD-K5 processor are precise, including those encountered in repeated string operations, which trap after completing the iteration on which the break- point match occurs.
Page 373: Debug Compatibility With Pentium Processor
7.5.3 Debug Compatibility with Pentium Processor The differences in debug functions between the AMD-K5 and Pentium processors are described in Section A.7 on page A-15. Branch Tracing Branch tracing is enabled by writing bits 3–1 with 001b and set- ting bit 5 to 1 in the Hardware Configuration Register (HWCR), as described in Section 7.1 on page 7-3.
Page 374: Table 7-4. Branch-Trace Message Special Bus Cycle Fields
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table 7-4. Branch-Trace Message Special Bus Cycle Fields Signals First Special Bus Cycle Second Special Bus Cycle 0 = first special bus cycle (source) 1 = second special bus cycle (target) Operating Mode of Target: 11 = Virtual-8086 Mode A30–A29...
Page 375: Boundary-Scan Test Access Port (Tap)
No action other than the assertion of IERR is taken by the proces- sor. On the AMD-K5 processor, the IERR output is reserved solely for functional-redundancy checking. No other errors are reported on that output.
Page 376 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 The TAP consists of the following: Test Access Port (TAP) Controller—A synchronous, finite state machine that decodes the inputs on the TMS signal to control a sequence of test operations. Instruction Register (IR)—Accepts serially shifted instruc- tions from the TDI input.
Page 377: Table 7-5. Test Access Port (Tap) Id Code
(update_DR or update_IR). The sections below describe only those aspects of the IEEE standard that are implemented uniquely by the AMD-K5 pro- cessor. For a description of the IEEE-mandatory TAP functions and the IEEE optional functions implemented by the AMD-K5 processor, see the IEEE Standard Test Access Port and Boundary- Scan Architecture (IEEE 1149.1-1990) specification.
Page 378: Table 7-6. Public Tap Instructions
As defined by the IEEE standard BYPASS 11111 As defined by the IEEE standard Undefined instruction encodings select the BYPASS BYPASS undefined instruction Notes: 1. Documentation on the Hardware Debug Tool (HDT) is available from AMD under a nondisclosure agreement. 7-22 Test and Debug...
Page 379: Hardware Debug Tool (Hdt)
Port (TAP) instruction register with the USEHDT instruction. Documentation on the HDT is available under nondisclosure agreement to test and debug developers. For information, con- tact your AMD sales representative or field application engi- neer. Hardware Debug Tool (HDT) 7-23...
Page 380 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 7-24 Test and Debug...
Page 381 Pentium and AMD-K5 processors. This appendix describes these differences. (For the most current list of differences, see the Comparison of the AMD-K5 and Pen- tium Processors application note, order# 20025.)
Page 382: A.1 Bus Signals
18524C/0—Nov1996 Bus Signals A.1.1 Signal Comparison Table A-1 compares the signals on the Pentium processor with those on the AMD-K5 processor, showing which signals are sup- ported on each processor. Table A-1. AMD-K5 and Pentium Processor Signal Comparison Pentium Signal...
Page 383 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table A-1. AMD-K5 and Pentium Processor Signal Comparison (continued) Pentium Signal (735\90, AMD-K5 Function 815\100) System Clock (5 V-tolerant) CPUTYP Primary or Secondary Processor Data or Code Cycle D63–D0 Data Bus Dual or Primary Processor Cycle DP7–DP0...
Page 384 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Table A-1. AMD-K5 and Pentium Processor Signal Comparison (continued) Pentium Signal (735\90, AMD-K5 Function 815\100) PBREQ Private Bus Request Page Cache Disable PCHK Parity Check Parity Enable PHIT Private Hit PHITM Private Hit to Modified Line...
Page 385: A.2 Bus Interface
If the Accessed bit needs to be set, two locked reads will be followed by one 1-byte locked write. For updates to the Busy bit in the TSS descriptor, the AMD-K5 processor behaves in the manner described for updates to the Accessed bit.
Page 386: A.2.3 Bus Cycle Order Of Misaligned Memory And I/O Cycles
A.2.4 Halt Cycle after FLUSH When halted, the AMD-K5 processor reruns a Halt special cycle after the Flush Acknowledge special cycle following a cache flush operation. The Pentium processor does not rerun a Halt special cycle.
Page 387: Comments
AMD-K5 processor Drive Strength 2 is between the Pentium processor Drive Strength medium and strong The only way to get the AMD-K5 processor Drive Strength 2 is to select the Pentium processor Drive Strength strong (as shown in the table above)
Page 388: A.3 Bus Mastering Operations (Including Snooping)
BOFF or AHOLD or both asserted, the Pentium processor treats the snoop as a hit, whereas the AMD-K5 processor may or may not treat it as a hit. For DCACHE linefills, the AMD-K5 processor treats the snoop...
Page 389: A.3.3 Snoop Before Write Hit To Icache Appears On Bus
Model 1 of the AMD-K5 processor does not have the difference. Comments In treating the snoop as a hit, the AMD-K5 and Pentium proces- sors assert the HIT pin and also cache the line as either shared or invalid, depending on the state of the INV pin. The cycle restarts after the deassertion of BOFF and AHOLD.
Page 390: A.3.5 Cache Line Ownership
However, if two or more writes to different locations within the same cache line are queued up in the store buffer, the line is shared and the WB/WT pin is set High, then the AMD-K5 pro- cessor correctly allows the first write to reach the bus and the line transitions to exclusive.
Page 391: A.4 Memory Management
The Pentium processor performs speculative TLB refills (including setting the accessed bit) for code prefetches. This may result in the accessed bit being set for a page that is not actually used. The AMD-K5 processor does not perform specu- lative TLB refills. A.4.2...
Page 392: A.5 Power Saving Features
I/O instructions, where the timing of the SMI met the requirements for SMI I/O trapping. On the AMD-K5 processor, if, on the RSM, the I/O Restart Flag in the SMM save area is set, the debug trap is cancelled and will be redetected as a result of the reexecution of the I/O instruction.
Page 393: A.5.4 Smm Save Area
AMD-K5 and Pentium processors. In addi- tion, the AMD-K5 and the Pentium processors store the IDT base at different locations in the SMM save area. The AMD-K5 processor stores the IDT base at offset 7F94h, and the Pentium processor stores it at offset 7F90h.
Page 394: A.6 Exceptions
486 processors prioritize the limit violation fault. A.6.2 Task Switch On a task switch, the AMD-K5 processor sets the busy bit of the incoming task after storing the outgoing TSS according to 486 and Pentium processor documentation. The Pentium processor sets the busy bit before trying to store the outgoing TSS.
Page 395: A.7 Debug
Multiple Debug Breakpoint Matches Multiple debug breakpoint matches on a single memory access do not set multiple DR6.B bits on the AMD-K5 processor. The Pentium processor may set multiple B-bits, regardless of whether the additional matching debug registers are enabled.
Page 396 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 A-16...
Page 397 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Index Numerics DDC ....... . 7-4 DE .
Page 398 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 speed......5-139, 6-9 invalidations ....2-16–2-17 turnaround .
Page 399 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 DBP ........7-4 timing .
Page 400 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 HOLD ... . . 5-8, 5-76, 5-166, 5-168, 6-19 performance......4-1 HWCR .
Page 401 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Invalidation......5-88 TLBs ....... 2-28 buffer .
Page 402 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Parity ......5-8–5-9 address ....5-31–5-32, 5-157 R/S .
Page 403 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 Signals M/IO ..... . 5-8, 5-95, 5-136 A20M ..... . 5-8, 5-18, 6-22 NA .
Page 404 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 global page extension (GPE) . 3-3, 3-8–3-9, 3-11 I/O breakpoints ..... . 7-16 Tags interrupt redirection bitmap (IRB) .
Page 405 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 WBINVD ......5-35, 5-180 Weak Memory Order ....2-26 Undefined Flags .
Page 406 AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996 I-10 Index...

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Amd-k5

AMD K5 Technical Reference Manual

1 Overview

2 Internal Architecture

3 Software Environment and Extensions

4 Performance

5 Bus Interface

6 System Design

7 Test and Debug

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