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Summary of Contents for AMD ATHLON K
- Page 1 Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide Publication # 23614 Rev: K Issue Date: October 2003...
- Page 2 Trademarks AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, AMD-751, and AMD-756 are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Page 3: Revision History
Added errata #21–23. July 2002 Added erratum #20. March 2002 Added erratum #17. Removed OPN information. Added errata items 13, 14, 15, 16. Added information on silicon April 2001 revision A9. Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide Description... - Page 4 AMD Athlon™ Processor Model 4 Revision Guide AMD Athlon™ Processor Model 4 The purpose of the AMD Athlon™ Processor Model 4 Revision Guide is to communicate updated product information on the AMD Athlon™ processor model 4 to designers of computer systems and software developers.
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Page 5: Table Of Contents
23614K—October 2003 Product Errata This section documents AMD Athlon processor model 4 product errata. The errata are divided into categories to assist referencing particular errata. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. -
Page 6: Mca Bus Unit Control Register Msr 408H Returns Incorrect Information
Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 MCA Bus Unit Control Register MSR 408H Returns Incorrect Information Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. System reads to MSR 408h, MCA Bus Unit Control Register MC2_CTL, should return correct information—the lower 32 bits in EAX and all zeros for the upper 32 bits in EDX. -
Page 7: Resistance Value Of The Zn And Zp Pins
Resistance Value of the ZN and ZP Pins Products Affected. A4, A5 Normal Specified Operation. The ZN and ZP pins are specified such that the AMD system bus output drivers autocompensate to whatever resistance value is applied between ZN and VDD and ZP and VSS. -
Page 8: Pll Overshoot On Wake-Up From Disconnect Causes Auto-Compensation Circuit To Fail
PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. The AMD Athlon processor model 4 PLL should return to the normal operating frequency when reconnecting to the system bus after a disconnect where the PLL was reduced to a lower operating frequency. -
Page 9: Instruction Execution Deadlock
Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 Instruction Execution Deadlock Products Affected. A4, A5, A6, A7 Normal Specified Operation. Legitimate instruction sequences should execute as specified. Non-conformance. Under rare and unlikely conditions, the load-store unit, instruction scheduler and effective address generation unit interact in such a way that deadlock a occurs, preventing further instruction execution. -
Page 10: Processors With Half-Frequency Multipliers May Hang Upon Wake-Up From Disconnect
Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from Disconnect Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. The processor should reconnect to the system bus upon wake-up after a disconnect while in the C2 and C3 ACPI low-power states. -
Page 11: Processor Does Not Support Reliable Microcode Patch Mechanism
Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 Processor Does Not Support Reliable Microcode Patch Mechanism Products Affected. A9 Normal Specified Operation. The processor should function properly after a microcode patch is loaded. Non-conformance. The processor has the patch RAM BIST function disabled. Since BIST is not run on the patch RAM, reliable operation of the patch RAM cannot be assured. -
Page 12: Invlpg Instruction Does Not Flush Entire Four-Megabyte Page Properly With Certain Linear Addresses
AMD Athlon™ Processor Model 4 Revision Guide INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain Linear Addresses Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. After executing an INVLPG instruction the TLB should not contain any translations for any part of the page frame associated with the designated logical address. -
Page 13: Code Modifications That Coincide With Level 2 Instruction Tlb Translations May Escape Detection Resulting In Stale Code Execution
Potential Effect on System. Stale code will be executed resulting in unpredictable system behavior. Suggested Workaround. Consult with your platform vendor for a BIOS that works around this erratum. Resolution Status. No fix planned. Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide... - Page 14 AMD Athlon™ Processor Model 4 Revision Guide A Speculative SMC Store Followed by an Actual SMC Store May Cause One-Time Stale Execution Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Self-modifying code sequences should be correctly detected and handled in a manner consistent with canonical results;...
- Page 15 Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Illegal values of ECX (that is, ECX>3) for the RDPMC (Read Performance Monitor Counter) instruction cause the processor to take a general protection exception.
- Page 16 Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Task gates should correctly use the TSS selector out of the task gate for CALL and JMP instructions.
- Page 17 Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 Single Step Across I/O SMI Skips One Debug Trap Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. When single stepping (with EFLAGS.TF) across an IN or OUT instruction that detects an SMI, the processor correctly defers taking the debug trap and instead enters SMM.
- Page 18 AMD Athlon™ Processor Model 4 Revision Guide Software Prefetches May Report A Page Fault Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Software prefetches should not report page faults if they encounter them. Non-conformance. Software prefetch instructions are defined to ignore page faults. Under highly specific...
- Page 19 For example, if the address desired to be prefetched is "ADDR", use an offset of 0x33 to compute the address used by the actual prefetch instruction as: "(ADDR & ~0x3f) + 0x33". Resolution Status. No fix planned. Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide...
- Page 20 AMD Athlon™ Processor Model 4 Revision Guide Revision Determination Table 2 shows the AMD Athlon processor model 4 identification number returned by the CPUID instruction for each revision of the processor. Table 2. CPUID Values for the Revisions of the AMD Athlon™ Processor Model 4...
- Page 21 AMD-756™ Peripheral Bus Controller Data Sheet, order# 22548 ■ AMD Athlon™ Processor x86 Code Optimization Guide, order# 22007 For the latest updates, refer to www.amd.com and download the appropriate files. For documents under NDA, please contact your local sales representative for updates. Preliminary Information...
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