AMD M56 Reference Manual page 404

Table A-8 Memory Controller Registers Sorted by Name
MC_SEQ_MISC_TIMING
MC_SEQ_NPL_CTL_I0
MC_SEQ_NPL_CTL_I1
MC_SEQ_QS_PAD_CNTL_I0
MC_SEQ_QS_PAD_CNTL_I1
MC_SEQ_RAS_TIMING
M56 Register Reference Manual
A-44
Register Name
MC_SEQ_DRAM
MC_SEQ_IO_CTL_I0
MC_SEQ_IO_CTL_I1
MC_SEQ_RD_CTL_I0
MC_SEQ_RD_CTL_I1
MC_SEQ_STATUS
MC_SEQ_WR_CTL_I0
MC_SEQ_WR_CTL_I1
MC_STATUS
MC_SW_CNTL
MC_TIMING_CNTL_2
MC_VENDOR_ID_I0
MC_VENDOR_ID_I1
MC_WRITE_AGE1
MC_WRITE_AGE2
(Continued)
Address
MCIND:0x60
MCIND:0x68
MCIND:0x69
MCIND:0x63
MCIND:0x6A
MCIND:0x6B
MCIND:0x72
MCIND:0x73
MCIND:0x61
MCIND:0x64
MCIND:0x65
MCIND:0x77
MCIND:0x66
MCIND:0x67
MCIND:0x0
MCIND:0x18
MCIND:0x3
MCIND:0x98
MCIND:0x99
MCIND:0x37
MCIND:0x38
© 2007 Advanced Micro Devices, Inc.
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