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Field Name
RX_NUM_NACK
the number of Nak received
Field Name
RX_NUM_NACK_GENERATED
The number of Nak generated
Field Name
RX_ACK_NACK_LATENCY
ACK/NACK Latency
PCIE_RX_ACK_NACK_LATENCY_THRESHOLD - R - 32 bits - PCIEIND:0x74
Field Name
RX_ACK_NACK_LATENCY_TH
Field Name
RX_TLP_HDR0
RX TLP Header Register
Field Name
RX_TLP_HDR1
RX TLP Header Register
Field Name
RX_TLP_HDR2
RX TLP Header Register
Field Name
RX_TLP_HDR3
© 2007 Advanced Micro Devices, Inc.
Proprietary
Bits
31:0
PCIE_RX_NUM_NACK_GENERATED - R - 32 bits - PCIEIND:0x72
Bits
31:0
PCIE_RX_ACK_NACK_LATENCY - R - 32 bits - PCIEIND:0x73
Bits
31:0
Bits
31:0
PCIE_RX_TLP_HDR0 - R - 32 bits - PCIEIND:0x75
Bits
31:0
PCIE_RX_TLP_HDR1 - R - 32 bits - PCIEIND:0x76
Bits
31:0
PCIE_RX_TLP_HDR2 - R - 32 bits - PCIEIND:0x77
Bits
31:0
PCIE_RX_TLP_HDR3 - R - 32 bits - PCIEIND:0x78
Bits
31:0
Default
0x0
The number of Nak received from the time of Power up, hot reset, or
link-dn
Default
0x0
The number of Nak generated from the time of Power up, hot reset,
or link-dn
Default
0x0
The number of cycles between the receiving the a tlp and to send
back a Ack/Nak. this register is for debugging only
Default
0x0
ACK/NACK Latency Threshold
Default
0x0
Contents of the last received TLP Header (bits 31:0)
Default
0x0
Contents of the last received Header (bits 63:32)
Default
0x0
Contents of the last received TLP Header (bits 95:64)
Default
0x0
Contents of the last received TLP Header (bits 127:96)
Bus Interface Registers
Description
Description
Description
Description
Description
Description
Description
Description
M56 Register Reference Manual
2-91
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