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SLOT_CLOCK_CFG
The Link Status register provides information about PCI Express Link specific parameters.
Field Name
MSI_CAP_ID
MSI Capability ID.
Field Name
MSI_NXT_CAP_PTR
MSI Next Capability Pointer.
Field Name
MSI_EN
MSI_MULTMSG_CAP (R)
MSI_MULTMSG_EN
MSI_64BIT (R)
MSI Message Control register.
Field Name
MSI_MSG_ADDR_LO
MSI Message Lower Address. MSI is assumed to be in 64 bit mode all the time.
© 2007 Advanced Micro Devices, Inc.
Proprietary
12
MSI_CAP_ID - R - 8 bits - [CFGF0_DEC:0x80] [HIDEC:0x5080]
Bits
7:0
MSI_NXT_CAP_PTR - R - 8 bits - [CFGF0_DEC:0x81] [HIDEC:0x5081]
Bits
7:0
MSI_MSG_CNTL - RW - 16 bits - [CFGF0_DEC:0x82] [HIDEC:0x5082]
Bits
0
3:1
6:4
7
MSI_MSG_ADDR_LO - RW - 32 bits - [CFGF0_DEC:0x84] [HIDEC:0x5084]
Bits
31:2
0x1
0=Different Clock
1=Same Clock
Default
0x5
MSI Capability ID
Default
0x0
The last item in capabilities list.
Default
0x0
Enable MSI messaging
0=Disable
1=Enable
0x0
Multiple Message Capable register is read to determine the number
of requested messages.
0=1 message allocated
1=2 messages allocated
2=4 messages allocated
3=8 messages allocated
4=16 messages allocated
5=32 messages allocated
6=Reserved
7=Reserved
0x0
Multiple Message Enable register is written to indicate the number of
allocated messages.
0=1 message allocated
1=2 messages allocated
2=4 messages allocated
3=8 messages allocated
4=16 messages allocated
5=32 messages allocated
6=Reserved
7=Reserved
0x0
Signifies if a device function is capable of generating a 64-bit mes-
sage address
0=Not capable of generating 1 64-bit message address
1=Capable of generating 1 64-bit message address
Default
0x0
System-specified message lower address.
Bus Interface Registers
Description
Description
Description
Description
M56 Register Reference Manual
2-69
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