Clock Registers Sorted By Name - AMD M56 Reference Manual

A.4

Clock Registers Sorted by Name

Table A-3 Clock Registers Sorted by Name
CLOCK_CNTL_INDEX
DYN_BACKBIAS_CNTL
DYN_PWRMGT_SCLK_CNTL
DYN_PWRMGT_SCLK_LENGTH
DYN_SCLK_PWMEN_PIPE
DYN_SCLK_VOL_CNTL
MC_HOST_DYN_CNTL
MCLK_PWRMGT_CNTL
MPLL_BYPASSCLK_SEL
SCLK_PWRMGT_CNTL
SPLL_BYPASSCLK_SEL
M56 Register Reference Manual
A-8
Register Name
CG_CLKPIN_CNTL
CG_MISC_REG
CG_TC_JTAG_0
CG_TC_JTAG_1
CLOCK_CNTL_DATA
DLL_CNTL
ERROR_STATUS
GENERAL_PWRMGT
MC_GUI_DYN_CNTL
MC_RBS_DYN_CNTL
MCLK_MISC
MPLL_CLK_SEL
MPLL_CNTL_MODE
MPLL_FUNC_CNTL
MPLL_TIME
PLL_TEST_CNTL
POLARITY_CNTL
SPLL_CLK_SEL
SPLL_CNTL_MODE
SPLL_FUNC_CNTL
SPLL_TIME
TCL_DYN_CNTL
VIP_DYN_CNTL
VOL_DROP_CNT
Address
CLKIND:0x3C
CLKIND:0x1F
CLKIND:0x38
CLKIND:0x39
CGDEC:0xE00C
CGDEC:0xE008
CLKIND:0x23
CLKIND:0x29
CLKIND:0xB
CLKIND:0xC
CLKIND:0xD
CLKIND:0xE
CLKIND:0x2C
CLKIND:0x8
CLKIND:0x1D
CLKIND:0x1E
CLKIND:0x26
CLKIND:0x22
CLKIND:0xA
CLKIND:0x5
CLKIND:0x7
CLKIND:0x6
CLKIND:0x4
CLKIND:0x25
CLKIND:0x21
CLKIND:0x2A
CLKIND:0x9
CLKIND:0x1
CLKIND:0x3
CLKIND:0x2
CLKIND:0x0
CLKIND:0x24
CLKIND:0x1A
CLKIND:0x14
CLKIND:0x36
© 2007 Advanced Micro Devices, Inc.
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