AMD M56 Reference Manual page 141

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CAP0_VBI2_INT_AK (W)
CAP0_VBI3_INT (R)
CAP0_VBI3_INT_AK (W)
CAP0_ANC2_INT (R)
CAP0_ANC2_INT_AK (W)
CAP0_ANC3_INT (R)
CAP0_ANC3_INT_AK (W)
Capture port interrupt control.
© 2007 Advanced Micro Devices, Inc.
Proprietary
9
0x0
VBI buffer 2 interrupt acknowledgment.
0=No effect
1=Clear status
10
0x0
Read only. VBI buffer 3 interrupt status.
0=No event
1=Event has occurred, interrupting if enabled
10
0x0
VBI buffer 3 interrupt acknowledgment.
0=No effect
1=Clear status
11
0x0
Read only. ANC buffer 2 interrupt status.
0=No event
1=Event has occurred, interrupting if enabled
11
0x0
ANC buffer 2 interrupt acknowledgment.
0=No effect
1=Clear status
12
0x0
Read only. ANC buffer 3 interrupt status.
0=No event
1=Event has occurred, interrupting if enabled
12
0x0
ANC buffer 3 interrupt acknowledgment.
0=No effect
1=Clear status
VIP/I2C Registers
M56 Register Reference Manual
2-135

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