AMD M56 Reference Manual page 340

Display Output Registers
DACA_CAPTURE_START_INT_EN
DACB_CAPTURE_START_INT_EN
TMDSA_CAPTURE_START_INT_EN
LVTMA_CAPTURE_START_INT_EN
DVOA_CAPTURE_START_INT_EN
DACA_CAPTURE_START_STATUS (R)
DACB_CAPTURE_START_STATUS (R)
TMDSA_CAPTURE_START_STATUS (R)
LVTMA_CAPTURE_START_STATUS (R)
DVOA_CAPTURE_START_STATUS (R)
Capture Start Control
Field Name
SYNC_STRENGTH_SN
SYNC_STRENGTH_SP
Field Name
STRENGTH_SN
STRENGTH_SP
PWRSEQ_STRENGTH_SN
PWRSEQ_STRENGTH_SP
Field Name
M56 Register Reference Manual
2-334
10
11
12
13
14
15
16
17
18
19
DC_GPIO_PAD_STRENGTH_1 - RW - 32 bits - DISPDEC:0x7ED4
Bits Default
27:24
31:28
DC_GPIO_PAD_STRENGTH_2 - RW - 32 bits - DISPDEC:0x7ED8
Bits Default
3:0
7:4
19:16
23:20
DISP_INTERRUPT_STATUS - RW - 32 bits - DISPDEC:0x7EDC
Bits Default
0x0 Enable interrupts on DACA Capture Start. Interrupt can be monitored
by polling
DISP_INTERRUPT_STATUS.DACA_CAPTURE_START_INTERRU
PT.
0=Disable
1=Enable
0x0 Enable interrupts on DACB Capture Start. Interrupt can be monitored
by polling
DISP_INTERRUPT_STATUS.DACB_CAPTURE_START_INTERRU
PT.
0=Disable
1=Enable
0x0 Enable interrupts on TMDSA Capture Start. Interrupt can be moni-
tored by polling
DISP_INTERRUPT_STATUS.TMDSA_CAPTURE_START_INTERR
UPT.
0=Disable
1=Enable
0x0 00 - Disable
01 - Enable
0x0 Enable interrupts on DVOA Capture Start. Interrupt can be monitored
by polling
DISP_INTERRUPT_STATUS.DVOA_CAPTURE_START_INTERRU
PT.
0=Disable
1=Enable
0x0 Capture Start used by DACA.
0x0 Capture Start used by DACB.
0x0 Capture Start used by TMDSA.
0x0 Capture Start used by LVTMA.
0x0 Capture Start used by DVOA.
0x7 Control SN strengths for HSYNCA, HSYNCB, VSYNCA & VSYNCB
0x4 Control SP strengths for HSYNCA, HSYNCB, VSYNCA & VSYNCB
0x7 Control SN strengths for DDC1, DDC2, DDC3, GENERICA, GENER-
ICB, GENERICC, HPD1 & HPD2 pads
0x4 Control SP strengths for DDC1, DDC2, DDC3, GENERICA, GENER-
ICB, GENERICC, HPD1 & HPD2 pads
0x7 Control SN strengths for BLON & DIGON pads
0x4 Control SP strengths for BLON & DIGON pads
© 2007 Advanced Micro Devices, Inc.
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