AMD M56 Reference Manual page 68

Bus Interface Registers
PARITY_ERROR_DETECTED
Status register.
Field Name
MINOR_REV_ID
MAJOR_REV_ID
Revision ID register.
Field Name
REG_LEVEL_PROG_INF
Register-Level Programming Interface Register
Field Name
SUB_CLASS_INF
Sub Class Register
Field Name
BASE_CLASS_CODE
Base Class Code Register
Field Name
CACHE_LINE_SIZE
CacheLine Size register.
Field Name
LATENCY_TIMER
Latency Timer register.
M56 Register Reference Manual
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REVISION_ID - R - 8 bits - [CFGF0_DEC:0x8] [HIDEC:0x5008]
Bits Default
3:0
7:4
REGPROG_INF - R - 8 bits - [CFGF0_DEC:0x9] [HIDEC:0x5009]
Bits Default
7:0
SUB_CLASS - R - 8 bits - [CFGF0_DEC:0xA] [HIDEC:0x500A]
Bits Default
7
BASE_CODE - R - 8 bits - [CFGF0_DEC:0xB] [HIDEC:0x500B]
Bits Default
7:0
CACHE_LINE - RW - 8 bits - [CFGF0_DEC:0xC] [HIDEC:0x500C]
Bits Default
7:0
LATENCY - R - 8 bits - [CFGF0_DEC:0xD] [HIDEC:0x500D]
Bits Default
7:0
0x0 This bit is set when a device sends an ERR_FATAL or
ERR_NONFATAL Message, and the SERR Enable bit in the Com-
mand register is 1.
0x0 Major revision ID. Set by the vendor.
0x0 Minor revision ID. Set by the vendor.
0x0 Unused, only in test environment
0x0 The Sub Class Code register is read-only and is used to identify a
more specific function of the device.
0=VGA device
1=Extended graphics
0x3 The Class Code register is read-only and is used to identify the
generic function of the device.
0x0 This read/write register specifies the system cacheline size in units of
DWORDs.
0x0 Primary/Master latency timer does not apply to PCI Express. Regis-
ter is hardwired to 0.
© 2007 Advanced Micro Devices, Inc.
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