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LVDS Registers
Field Name
LVTMA_DSYNSEL
LVTMA_PFREQCHG (W)
LVTMA Data Sychronization Control
Field Name
LVTMA_CTL0_DATA_SEL
LVTMA_CTL0_DATA_DELAY
LVTMA_CTL0_DATA_INVERT
LVTMA_CTL0_DATA_MODULATION
LVTMA_CTL0_USE_FEEDBACK_PATH
LVTMA_CTL0_FB_SYNC_CONT
LVTMA_CTL0_PATTERN_OUT_EN
LVTMA_CTL1_DATA_SEL
LVTMA_CTL1_DATA_DELAY
M56 Register Reference Manual
2-346
LVTMA_DATA_SYNCHRONIZATION - RW - 32 bits - DISPDEC:0x7AD8
Bits
0
8
LVTMA_CTL0_1_GEN_CNTL - RW - 32 bits - DISPDEC:0x7ADC
Bits
3:0
6:4
7
9:8
10
11
12
19:16
22:20
Default
0x0
Data synchronization circuit select enable
0=Disable
1=Enable
0x0
Write to 1 to restarts read and write address generation logic. Write of
0 has no effect. Read value is always 0. PFREQCHG must be written
to 1 when the data synchronizer is started by setting DSYNSEL to 1,
whenever LVTMA_DUAL_LINK_ENABLE is reprogrammed, or either
PCLK_LVTMA or PCLK_LVTMA_DIRECT (IDCLK) is reprogrammed
or stopped and restarted.
Default
0x0
Select data to be used to generate CTL0 pattern (selected fields are
ORed together)
[0]: Display Enable
[1]: VSYNC
[2]: HSYNC
[3] Random data
0x0
Number of pixel clocks to delay CTL0 data
0=CTL0 data is delayed 0 pixel clocks
1=CTL0 data is delayed 1 pixel clocks
2=CTL0 data is delayed 2 pixel clocks
3=CTL0 data is delayed 3 pixel clocks
4=CTL0 data is delayed 4 pixel clocks
5=CTL0 data is delayed 5 pixel clocks
6=CTL0 data is delayed 6 pixel clocks
7=CTL0 data is delayed 7 pixel clocks
0x0
Set to 1 to invert CTL0 data
0=CTL0 data is normal
1=CTL0 data is inverted
0x0
CTL0 data modulation control
0=CTL0 data is not modulated
1=CTL0 data is modulated by bit 0 of 2 bit counter
2=CTL0 data is modulated by bit 1 of 2 bit counter
3=CTL0 data is modulated every time 2 bit counter overflows
0x0
Set to 1 to enable CTL0 internal feedback path
0x0
Set to 1 to force continuous toggle on CTL0 internal feedback path
0x0
Select CTL0 output data
0=Register value
1=Pattern generator output
0x0
Select data to be used to generate CTL1 pattern (selected fields are
ORed together)
[0]: Display Enable
[1]: VSYNC
[2]: HSYNC
[3] Always (blank time)
0x0
Number of pixel clocks to delay CTL1 data
0=CTL1 data is delayed 0 pixel clocks
1=CTL1 data is delayed 1 pixel clocks
2=CTL1 data is delayed 2 pixel clocks
3=CTL1 data is delayed 3 pixel clocks
4=CTL1 data is delayed 4 pixel clocks
5=CTL1 data is delayed 5 pixel clocks
6=CTL1 data is delayed 6 pixel clocks
7=CTL1 data is delayed 7 pixel clocks
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
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