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Display Controller Registers
D1GRPH_SURFACE_UPDATE_PENDING (R)
D1GRPH_SURFACE_UPDATE_TAKEN (R)
D1GRPH_UPDATE_LOCK
Primary graphic update control
Field Name
D1GRPH_SURFACE_UPDATE_H_RETRACE_E
N
Enable primary graphic surface register double buffer in horizontal retrace
D1GRPH_SURFACE_ADDRESS_INUSE - RW - 32 bits - DISPDEC:0x614C
Field Name
D1GRPH_SURFACE_ADDRESS_INUSE (R)
Snapshot of primary graphics surface address in use
M56 Register Reference Manual
2-202
2
0x0
3
0x0
16
0x0
D1GRPH_FLIP_CONTROL - RW - 32 bits - DISPDEC:0x6148
Bits
Default
0
0x0
Bits
Default
31:11
0x0
Primary graphic surface register update pending control. If it is set to
1 after a host write to graphics surface register. It is cleared after dou-
ble buffering is done. It is cleared after double buffering is done.
This signal also goes to both the RBBM wait_until and to the
CP_RTS_discrete inputs.
The graphics surface register includes:
D1GRPH_PRIMARY_SURFACE_ADDRESS
D1GRPH_SECONDARY_SURFACE_ADDRESS
D1GRPH_PITCH
D1GRPH_SURFACE_OFFSET_X
D1GRPH_SURFACE_OFFSET_Y.
If D1GRPH_SURFACE_UPDATE_H_RETRACE_EN = 0, the double
buffering occurs in vertical retrace when
D1GRPH_SURFACE_UPDATE_PENDING = 1 and
D1GRPH_UPDATE_LOCK = 0 and V_UPDATE = 1. Otherwise the
double buffering happens at horizontal retrace when
D1GRPH_SURFACE_UPDATE_PENDING = 1 and
D1GRPH_UPDATE_LOCK = 0 and Data request for last chunk of the
line is sent from DCP to DMIF.
If CRTC1 is disabled, the registers will be updated instantly
Primary graphics update taken status for surface registers. If
D1GRPH_SURFACE_UPDATE_H_RETRACE_EN = 0, it is set to 1
when double buffering occurs and cleared when V_UPDATE = 0.
Otherwise, it is active for one clock cycle when double buffering
occurs at the horizontal retrace.
Primary graphic register update lock control. This lock bit control both
surface and mode register double buffer
0=Unlocked
1=Locked
Description
Enable primary graphic surface register double buffer in horizontal
retrace.
0=Vertical retrace flipping
1=Horizontal retrace flipping
Description
This register reads back snapshot of primary graphics surface
address used for data request. The address is the signal sent to
DMIF and is updated on SOF or horizontal surface update. The snap-
shot is triggered by writing 1 into field
D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC register
D1CRTC_SNAPSHOT_STATUS.
© 2007 Advanced Micro Devices, Inc.
Proprietary
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