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Table A-8 Memory Controller Registers Sorted by Name
MC_PT0_CLIENT0_CNTL
MC_PT0_CLIENT1_CNTL
MC_PT0_CLIENT10_CNTL
MC_PT0_CLIENT11_CNTL
MC_PT0_CLIENT12_CNTL
MC_PT0_CLIENT13_CNTL
MC_PT0_CLIENT14_CNTL
MC_PT0_CLIENT15_CNTL
MC_PT0_CLIENT16_CNTL
MC_PT0_CLIENT2_CNTL
MC_PT0_CLIENT3_CNTL
MC_PT0_CLIENT4_CNTL
MC_PT0_CLIENT5_CNTL
MC_PT0_CLIENT6_CNTL
MC_PT0_CLIENT7_CNTL
MC_PT0_CLIENT8_CNTL
MC_PT0_CLIENT9_CNTL
MC_PT0_CONTEXT0_CNTL
MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
MC_PT0_CONTEXT0_FLAT_BASE_ADDR
MC_PT0_CONTEXT0_FLAT_END_ADDR
MC_PT0_CONTEXT0_FLAT_START_ADDR
MC_PT0_CONTEXT0_MULTI_LEVEL_BASE_ADDR
MC_PT0_CONTEXT1_CNTL
MC_PT0_CONTEXT1_DEFAULT_READ_ADDR
MC_PT0_CONTEXT1_FLAT_BASE_ADDR
MC_PT0_CONTEXT1_FLAT_END_ADDR
MC_PT0_CONTEXT1_FLAT_START_ADDR
MC_PT0_CONTEXT1_MULTI_LEVEL_BASE_ADDR
MC_PT0_CONTEXT2_CNTL
MC_PT0_CONTEXT2_DEFAULT_READ_ADDR
MC_PT0_CONTEXT2_FLAT_BASE_ADDR
MC_PT0_CONTEXT2_FLAT_END_ADDR
MC_PT0_CONTEXT2_FLAT_START_ADDR
MC_PT0_CONTEXT2_MULTI_LEVEL_BASE_ADDR
MC_PT0_CONTEXT3_CNTL
MC_PT0_CONTEXT3_DEFAULT_READ_ADDR
MC_PT0_CONTEXT3_FLAT_BASE_ADDR
MC_PT0_CONTEXT3_FLAT_END_ADDR
M56 Register Reference Manual
A-42
Register Name
MC_MISC_0
MC_MISC_1
MC_NPL_STATUS_I0
MC_NPL_STATUS_I1
MC_PMG_CFG
MC_PMG_CMD
MC_PT0_CNTL
(Continued)
Address
MCIND:0xF0
MCIND:0xF1
MCIND:0x9A
MCIND:0x9B
MCIND:0xE1
MCIND:0xE0
MCIND:0x16C
MCIND:0x16D
MCIND:0x176
MCIND:0x177
MCIND:0x178
MCIND:0x179
MCIND:0x17A
MCIND:0x17B
MCIND:0x17C
MCIND:0x16E
MCIND:0x16F
MCIND:0x170
MCIND:0x171
MCIND:0x172
MCIND:0x173
MCIND:0x174
MCIND:0x175
MCIND:0x100
MCIND:0x102
MCIND:0x11C
MCIND:0x12C
MCIND:0x14C
MCIND:0x13C
MCIND:0x15C
MCIND:0x103
MCIND:0x11D
MCIND:0x12D
MCIND:0x14D
MCIND:0x13D
MCIND:0x15D
MCIND:0x104
MCIND:0x11E
MCIND:0x12E
MCIND:0x14E
MCIND:0x13E
MCIND:0x15E
MCIND:0x105
MCIND:0x11F
MCIND:0x12F
MCIND:0x14F
© 2007 Advanced Micro Devices, Inc.
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Proprietary
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