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Bus Interface Registers
PMI_DEV_SPECIFIC_INIT
PMI_D1_SUPPORT
PMI_D2_SUPPORT
PMI_PME_SUPPORT
Power Management Capabilities Register
Field Name
PMI_POWER_STATE
PMI_PME_EN (R)
PMI_DATA_SELECT (R)
PMI_DATA_SCALE (R)
PMI_PME_STATUS (R)
Power Management Status/Control Register
Field Name
B2_B3_SUPPORT
BPCC_EN
Power Management Bridge Support Extensions (BSE)
Field Name
PMI_DATA
Power Management Data Register
Field Name
CAP_ID
NEXT_PTR
The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 2.3 configuration space capability list.
Field Name
VERSION
DEVICE_TYPE
INT_MESSAGE_NUM
The PCI Express Capabilities register identifies PCI Express device type and associated capabilities.
Field Name
M56 Register Reference Manual
2-66
5
9
10
15:11
PMI_STATUS - RW - 16 bits - [CFGF0_DEC:0x54] [HIDEC:0x5054]
Bits
1:0
8
12:9
14:13
15
PMI_BSE - R - 8 bits - [CFGF0_DEC:0x56] [HIDEC:0x5056]
Bits
6
7
PMI_DATA - R - 8 bits - [CFGF0_DEC:0x57] [HIDEC:0x5057]
Bits
7:0
PCIE_CAP_LIST - R - 16 bits - [CFGF0_DEC:0x58] [HIDEC:0x5058]
Bits
7:0
15:8
PCIE_CAP - R - 16 bits - [CFGF0_DEC:0x5A] [HIDEC:0x505A]
Bits
3:0
7:4
13:9
DEVICE_CAP - R - 32 bits - [CFGF0_DEC:0x5C] [HIDEC:0x505C]
Bits
0x0
Device Specific Initialization
0x1
1=Support D1 Power Management State.
0x1
1=Support D2 Power Management State.
0x0
For a device, this indicates the power states in which the device may
generate a PME.
Default
0x0
Power State
0x0
PME Enable
0x0
Data Select
0x0
Data Scale
0x0
PME Status
Default
0x0
0=B2/B3 Support for D3Hot
0x0
0=Bus Power/Clock Control Enable
Default
0x0
Power Management Data Register
Default
0x10
10=PCI Express capable
0x80
Next Capability Pointer -- The offset to the next PCI capability struc-
ture or 00h if no other items exist in the linked list of capabilities.
Default
0x1
0=PCI Express Capabilities Version
0x0
0=PCI Express Endpoint
0x0
Interrupt Message Number.
Default
Description
Description
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
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