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Field Name
DEVICE_ID
Device ID register.
Field Name
IO_ACCESS_EN
MEM_ACCESS_EN
BUS_MASTER_EN
SPECIAL_CYCLE_EN (R)
MEM_WRITE_INVALIDATE_EN (R)
PAL_SNOOP_EN (R)
PARITY_ERROR_EN
AD_STEPPING (R)
SERR_EN
FAST_B2B_EN (R)
INT_DIS
Command register.
Field Name
INT_STATUS (R)
CAP_LIST (R)
PCI_66_EN (R)
UDF_EN (R)
FAST_BACK_CAPABLE (R)
MASTER_DATA_PARITY_ERROR
DEVSEL_TIMING (R)
SIGNAL_TARGET_ABORT (R)
RECEIVED_TARGET_ABORT
RECEIVED_MASTER_ABORT
SIGNALED_SYSTEM_ERROR
© 2007 Advanced Micro Devices, Inc.
Proprietary
DEVICE_ID - R - 16 bits - [CFGF0_DEC:0x2] [HIDEC:0x5002]
Bits
Default
15:0
COMMAND - RW - 16 bits - [CFGF0_DEC:0x4] [HIDEC:0x5004]
Bits
Default
0
1
2
3
4
5
6
7
8
9
10
STATUS - RW - 16 bits - [CFGF0_DEC:0x6] [HIDEC:0x5006]
Bits
Default
3
4
5
6
7
8
10:9
11
12
13
14
0x0
This field identifies the particular device. This identifier is allocated by
the vendor.
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Disable
1=Enable
0x0
0=Enable
1=Disable
0x0
Indicates that an INTx interrupt Message is pending internally to the
device.
0x1
Indicates the presence of an extended capability list item. Since all
PCI Express devices are required to implement the PCI Express
capability structure, this bit must be set to 1.
0x0
Does not apply to PCI Express. Hardwired to 0.
0x0
0=Disable
1=Enable
0x0
Does not apply to PCI Express. Hardwired to 0.
0x0
0=Inactive
1=Active
0x0
Does not apply to PCI Express. Hardwired to 0.
0x0
This bit is set when a device completes a Request using Completer
Abort Completion Status.
0x0
0=Inactive
1=Active
0x0
0=Inactive
1=Active
0x0
This bit must be set whenever the device asserts SERR#.
Bus Interface Registers
Description
Description
Description
M56 Register Reference Manual
2-61
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