AMD XILINX T2 Telco Installation Manual
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AMD XILINX T2 Telco Installation Manual

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T2 Telco Accelerator Card
Installation Guide
UG1527 (v1.0) June 15, 2022
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Summary of Contents for AMD XILINX T2 Telco

  • Page 1 T2 Telco Accelerator Card Installation Guide UG1527 (v1.0) June 15, 2022 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve launched an internal initiative to remove language that could exclude people or reinforce historical biases, including terms embedded in our software and IPs.

  • Page 2: Table Of Contents

    Table of Contents Chapter 1: Introduction ....................4 Minimum System Requirements and Setup................5 Configuring the PCIe Slot Bifurcation..................5 Chapter 2: Card Information and Installation ..........10 Safety Instructions........................10 Electrostatic Discharge......................10 Before You Begin........................10 Installing the Card........................11 Chapter 3: Installing Additional Software ............
  • Page 3 Appendix A: Regulatory Compliance Statements ........33 FCC Class A Products.........................33 Safety............................33 EMC Compliance........................34 FCC Class A User Information....................34 VCCI Class A Statement......................35 Appendix B: Additional Resources and Legal Notices ......36 Xilinx Resources.........................36 Documentation Navigator and Design Hubs.................36 References..........................36 Revision History.........................

  • Page 4: Chapter 1: Introduction

    Chapter 1: Introduction Chapter 1 Introduction This document provides hardware and software installation procedures for the T2 Telco accelerator card along with a guide to the T2 skeleton design. The skeleton design is created specifically for the 16 nm Zynq ®...

  • Page 5: Minimum System Requirements And Setup

    Chapter 1: Introduction The T2 card turns a standard server into a virtual baseband unit with the performance, low latency, and power efficiency needed for O-RAN 5G deployments. The turnkey solution enables operators, system integrators, and OEMs to get to market quickly and to simplify the deployment of services at the edge.
  • Page 6 Chapter 1: Introduction 2. Wait until the monitor lists the shortcut keys, so you can navigate into the setup. The screen with the shortcut keys looks like the following figure. 3. Press F2 to open the system setup settings. 4. In the System Setup screen, select the System BIOS option as shown below. UG1527 (v1.0) June 15, 2022 www.xilinx.com Send Feedback...
  • Page 7 Chapter 1: Introduction 5. Select Integrated Devices. 6. In the menu that is displayed, scroll down until you get to Slot Bifurcation. It is on the second half of the page. UG1527 (v1.0) June 15, 2022 www.xilinx.com Send Feedback T2 Telco Accelerator Card Installation Guide...
  • Page 8 Chapter 1: Introduction 7. Click the required slot to change bifurcation. 8. Click Default Bifurcation and select x8x8 or x8 Bifurcation. This enables the T2 card in the slot with the correct communication over the PCI. Click the Back button in the lower right hand side of the screen.
  • Page 9 Chapter 1: Introduction 9. Return to the System BIOS screen and click the Back button again. 10. In the System BIOS Settings main menu screen, click Finish. 11. A popup window will show a warning, as shown below. Click Yes to save the changes you made.

  • Page 10: Chapter 2: Card Information And Installation

    Chapter 2: Card Information and Installation Chapter 2 Card Information and Installation Safety Instructions To ensure your personal safety and the safety of your equipment: • Keep your work area and the computer/server clean and clear of debris. • Before opening the computer/system cover, unplug the power cord. Electrostatic Discharge Electrostatic discharge (ESD) can damage electronic components when they are improperly handled, and can result in total or intermittent failures.

  • Page 11: Installing The Card

    Chapter 2: Card Information and Installation • Verify that the minimum card space is available to install your card. • Check for card compatibility with your system. Check system requirements such as power, bus type, and physical dimensions to support the card. Installing the Card The following procedure is a guide to T2 Telco accelerator card PCI x16 installation.

  • Page 12: Chapter 3: Installing Additional Software

    Chapter 3: Installing Additional Software Chapter 3 Installing Additional Software To run the T2 card skeleton design or other demos provided by Xilinx partners, install the following additional software on the server: • DPDK package. The supported versions are 18.11, 19.11, and 20.11. •...

  • Page 13: Chapter 4: T2 Factory Installed Image

    Chapter 4: T2 Factory Installed Image Chapter 4 T2 Factory Installed Image The T2 Telco accelerator card is preprogrammed with an image in the QSPIs that consists of two separate designs that support the Zynq UltraScale+ RFSoC (ZU48). Each of the designs provides simple connectivity from the host server to the card and the two devices.
  • Page 14 Chapter 4: T2 Factory Installed Image 2. Verify the SC firmware version. Execute ./sc_flash.sh get_sc_fw_version. A possible successful output is shown below: SC fw version: 01.02.00 3. Bring the card in FW_AVAILABLE mode. For the first time, execute ./sc_flash.sh <image_name> <bsl_password_file>. The expected output is as follows: "Please reboot the Host and re-run the command"...

  • Page 15: Chapter 5: T2 Base Software Design

    Chapter 5: T2 Base Software Design Chapter 5 T2 Base Software Design The T2 card skeleton design supports the ZU48 Zynq ® UltraScale+™ RFSoC on the card. The design provides connectivity with the ports on the board from the ZU48 device. The design allows you to test the connectivity from the host to the card to demonstrate that the board is fully functional.

  • Page 16: T2 Skeleton Design Package

    Chapter 5: T2 Base Software Design Figure 2: ZU48 Skeleton Design Connections PS DDR4 AXI MM Interconnect PL DDR4 DDR4 MIG PCIe Gen4 x8 QDMA Text H2C AXIS AXI4-Stream Interconnect C2H AXIS AXI4-Lite Config X26411-031722 T2 Skeleton Design Package The T2 card skeleton design package comes as a Git repository. The code is stored in different branches, with one separate branch for each supported DPDK version (18.11, 19.11, and 20.11).
  • Page 17 Chapter 5: T2 Base Software Design Figure 3: Git Branch Structure The following files are included: • build.sh: This script downloads all packages from the Internet and applies Xilinx patches. • compile.sh: This script is used to compile the additional host software required to run the design.

  • Page 18: Chapter 6: Running The Tests

    Chapter 6: Running the Tests Chapter 6 Running the Tests The setup of the skeleton design to test the T2 card is shown in the following figure. Figure 4: Test Setup The following sections describe each test, including the setup, running, and expected results. The primary objective of testing is to verify the following main interfaces, and then to verify data transfer by comparing the output with expectations: UG1527 (v1.0) June 15, 2022...

  • Page 19: Zu48 Zynq Ultrascale+ Rfsoc Pcie Loopback Test

    Chapter 6: Running the Tests • ZU48 Zynq UltraScale+ RFSoC PCIe x8 interface • ZU48 Zynq UltraScale+ RFSoC PS/PL DDR4 ZU48 Zynq UltraScale+ RFSoC PCIe Loopback Test The QDMA IP and DPDK driver are used to perform the PCIe loopback test. The host generates L2 frames with the help of the DPDK pktgen application.
  • Page 20 Chapter 6: Running the Tests Test Requirements • The throughput should be near to 45 Gb/s in TX and RX of the pktgen application. • There should not be any packet loss; RX and TX counts should be identical. • There should not be any mismatch in TX and RX packets. UG1527 (v1.0) June 15, 2022 www.xilinx.com Send Feedback...

  • Page 21: Ddr Read/Write Tests

    Chapter 6: Running the Tests DDR Read/Write Tests These tests allow you to read/write to the DDR memory in the board that is connected to the devices. This includes the Zynq UltraScale+ RFSoC PS/PL portion. Figure 5: DDR Read/Write Test Setup Test Procedure 1.
  • Page 22 Chapter 6: Running the Tests 2. Create a couple of text files for H2C and C2H with different content using the following commands: echo "PS DDR Test" > dma_test_input.txt echo "XXXXXXXX" > dma_test_output.txt 3. Run the test.sh in root, with init as argument, to initialize the DMA related drivers. 4.
  • Page 23 Chapter 6: Running the Tests Test Requirements • Contents of the text files for H2C and C2H should match after DMA transfers. UG1527 (v1.0) June 15, 2022 www.xilinx.com Send Feedback T2 Telco Accelerator Card Installation Guide...

  • Page 24: Test Application Guide And Address Map

    Chapter 6: Running the Tests • There should not be any error in the DMA transfers. Test Application Guide and Address Map The QMDA test application guide is available here. The address map used in the tests in this document is shown in the following figure. Figure 6: Address Map UG1527 (v1.0) June 15, 2022 www.xilinx.com...

  • Page 25: Chapter 7: Next Steps

    Chapter 7: Next Steps Chapter 7 Next Steps Contact your Xilinx sales representative for the reference designs that are currently available from Xilinx partners. If you are an application developer who wants to develop and deliver a customized solution on the T2 Telco accelerator card, the skeleton design described in this document is a starting point.

  • Page 26: Chapter 8: Dependencies/Known Issues

    Chapter 8: Dependencies/Known Issues Chapter 8 Dependencies/Known Issues This section lists the dependencies and known issues at this time. • If a pktgen test is not properly terminated, a cold restart (that is to say, a power cycle of the server) might be necessary.

  • Page 27: Chapter 9: Programming The Devices Using Jtag

    Chapter 9: Programming the Devices Using JTAG Chapter 9 Programming the Devices Using JTAG The T2 card is preprogrammed with an image that allows you to use the flash application (flash_app) to program the QSPI flash memories that are connected to the Zynq UltraScale+ RFSoC ZU48 device.
  • Page 28 Chapter 9: Programming the Devices Using JTAG Figure 7: ADK Ribbon Cable Connection Connect the ADK ribbon cable as shown in the following figure. UG1527 (v1.0) June 15, 2022 www.xilinx.com Send Feedback T2 Telco Accelerator Card Installation Guide...
  • Page 29 Chapter 9: Programming the Devices Using JTAG Figure 8: Connected ADK Ribbon Cable Backside To complete the setup, connect the ribbon cable to the ADK card, then connect the ADK card to a micro USB cable so that it can connect to a computer that can run the Xilinx tools. The full connection is shown below.

  • Page 30: Flashing The Images To Zu48 Zynq Ultrascale+ Rfsoc Qspi Using The Vitis Environment

    Chapter 9: Programming the Devices Using JTAG The following figure shows the T2 card installed into a server, with the ADK cable attached and the micro USB cable going out of the back of the server. This setup allows the USB to be connected to an external laptop running on the server.

  • Page 31: Programming The Bitstreams Directly

    Chapter 9: Programming the Devices Using JTAG 1. Ensure that an ADK cable is connected between the ADK connector on the T2 card and the USB port on the host machine. The T2 with an ADK connected is shown in Chapter 9: Programming the Devices Using JTAG.
  • Page 32 Chapter 9: Programming the Devices Using JTAG 1. Disable the PCIe slot in BIOS settings using the iDRAC GUI. 2. Perform a warm reboot on the host machine. 3. Program the bitstream using Vivado Hardware Manager as shown in the following figure for the ZU48 device.

  • Page 33: Appendix A: Regulatory Compliance Statements

    Appendix A: Regulatory Compliance Statements Appendix A Regulatory Compliance Statements FCC Class A Products The products referred to in this document are listed below: • TA-T2-P6G-PQ-EV • TA-T2-P6G-PQ-DV Note: These devices are for use with UL Listed Servers or I.T.E. Regulatory compliance statements are valid for the production version of this product;...

  • Page 34: Emc Compliance

    Appendix A: Regulatory Compliance Statements EMC Compliance Class A Products The following standards apply: • FCC Part 15 – Radiated & Conducted Emissions (USA) • CAN ICES-3(A)/NMB-3(A) – Radiated & Conducted Emissions (Canada) • CISPR 32 – Radiated & Conducted Emissions (International) •...

  • Page 35: Vcci Class A Statement

    Appendix A: Regulatory Compliance Statements 1. This device may not cause harmful interference. 2. This device must accept any interference received, including interference that may cause undesired operation. CAUTION! This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC rules.

  • Page 36: Appendix B: Additional Resources And Legal Notices

    Appendix B: Additional Resources and Legal Notices Appendix B Additional Resources and Legal Notices Xilinx Resources For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. Documentation Navigator and Design Hubs Xilinx ® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information.

  • Page 37: Revision History

    Appendix B: Additional Resources and Legal Notices 1. T2 Telco Accelerator Card Data Sheet (DS1000) 2. T2 Telco Accelerator Card User Guide (UG1496) Revision History The following table shows the revision history for this document. Section Revision Summary 06/15/2022 Version 1.0 Initial release.
  • Page 38 Appendix B: Additional Resources and Legal Notices AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN").

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