AMD M56 Reference Manual page 28

Memory Controller Registers
Channel 0's DLL delay control parameters (MADJ). DLL delay (ns) = (ADJ[7:0]+24)/MADJ[7:0]*HCLK period
Field Name
MADJ0
MADJ1
MADJ2
MADJ3
Channel 1's DLL delay control parameters (MADJ). DLL delay (ns) = (ADJ[7:0]+24)/MADJ[7:0]*HCLK period
Field Name
DLY0
DLY1
DLY2
DLY3
Channel 0's DLL delay control parameters (ADJ). DLL delay (ns) = (ADJ[7:0]+24)/MADJ[7:0]*HCLK period
Field Name
DLY0
DLY1
DLY2
DLY3
Channel 1's DLL delay control parameters (ADJ). DLL delay (ns) = (ADJ[7:0]+24)/MADJ[7:0]*HCLK period
Field Name
CK_DLY
CMD_DLY
ADR_DLY
Channel 0's delay line parameters clock/command/address bits
M56 Register Reference Manual
2-22
MC_IO_RD_DQ_CNTL_I1 - RW - 32 bits - MCIND:0x85
Bits Default
7:0 0x0
15:8 0x0
23:16 0x0
31:24 0x0
MC_IO_RD_QS_CNTL_I0 - RW - 32 bits - MCIND:0x86
Bits Default
7:0 0x0
15:8 0x0
23:16 0x0
31:24 0x0
MC_IO_RD_QS_CNTL_I1 - RW - 32 bits - MCIND:0x87
Bits Default
7:0 0x0
15:8 0x0
23:16 0x0
31:24 0x0
MC_IO_WR_CNTL_I0 - RW - 32 bits - MCIND:0x88
Bits Default
4:0 0x0
9:5 0x0
14:10 0x0
Description
Byte 0
Byte 1
Byte 2
Byte 3
Description
Byte 0
Byte 1
Byte 2
Byte 3
Description
Byte 0
Byte 1
Byte 2
Byte 3
Description
Clock delay
Command delay
Address delay
© 2007 Advanced Micro Devices, Inc.
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