AMD M56 Reference Manual page 202

VGA Registers
Field Name
VCRTC_IDX
(mirror bits 0:5 of
CRTC_EXT_CNTL:VCRTC_IDX_MASTER)
CRT Index Register
Field Name
VCRTC_DATA
CTRC Data Register
Field Name
VGA_ATI_LINEAR
VGA_128KAP_PAGING
VGA_TEXT_132
VGA_PACK_DIS
VGA_MEM_PS_EN
VCRTC_IDX_MASTER
VGA Extended control Register
Field Name
GRPH_IDX
GRPH Index Register
Field Name
GRPH_DATA
GRPH Data Register
M56 Register Reference Manual
2-196
CRTC8_IDX - RW - 8 bits - [DISPDEC:0x3B4] [DISPDEC:0x3D4]
Bits Default
5:0
CRTC8_DATA - RW - 8 bits - [DISPDEC:0x3B5] [DISPDEC:0x3D5]
Bits Default
7:0
CRTC_EXT_CNTL - RW - 32 bits - DISPDEC:0xE054
Bits Default
3
4
5
18
19
30:24
GRPH8_IDX - RW - 8 bits - DISPDEC:0x3CE
Bits Default
3:0
GRPH8_DATA - RW - 8 bits - DISPDEC:0x3CF
Bits Default
7:0
0x0 This index points to one of the internal registers of the CRT controller
(CRTC) at address 0x3?5, for the next CRTC read/write operation.
0x0 CRTC data indirect access
0x0 0=Disable
1=Enable
0x0 0=Normal
1=Enable
0x0 0=inActive
1=Active
0x0 0=Fast VGA write in packed modes
1=Normal VGA write in packed modes
0x0 0=Don't use MEM_VGA_WP_SEL and MEM_VGA_RP_SEL regis-
ters
1=Use MEM_VGA_WP_SEL and MEM_VGA_RP_SEL registers
0x0 Mirror of the vga crtc index as per VGA specified by IBM. The top bit
is unused
0x0 VGA graphics index as per VGA specified by IBM
0x0 GRPH data indirect access
© 2007 Advanced Micro Devices, Inc.
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