AMD M56 Reference Manual page 354

LVDS Registers
LVTMA_CTL3_DATA_DELAY
LVTMA_CTL3_DATA_INVERT
LVTMA_CTL3_DATA_MODULATION
LVTMA_CTL3_USE_FEEDBACK_PATH
LVTMA_CTL3_FB_SYNC_CONT
LVTMA_CTL3_PATTERN_OUT_EN
Field Name
LVTMA_PWRSEQ_REF_DIV
LVTMA_BL_MOD_REF_DIV
Field Name
LVTMA_PWRUP_DELAY1
LVTMA_PWRUP_DELAY2
LVTMA_PWRDN_DELAY1
LVTMA_PWRDN_DELAY2
Field Name
LVTMA_PWRDN_MIN_LENGTH
M56 Register Reference Manual
2-348
22:20 0x0
23 0x0
25:24 0x0
26 0x0
27 0x0
28 0x0
LVTMA_PWRSEQ_REF_DIV - RW - 32 bits - DISPDEC:0x7AE4
Bits Default
11:0 0x0
27:16 0x0
LVTMA_PWRSEQ_DELAY1 - RW - 32 bits - DISPDEC:0x7AE8
Bits Default
7:0 0x0
15:8 0x0
23:16 0x0
31:24 0x0
LVTMA_PWRSEQ_DELAY2 - RW - 32 bits - DISPDEC:0x7AEC
Bits Default
7:0 0x0
Number of pixel clocks to delay CTL3 data
0=CTL3 data is delayed 0 pixel clocks
1=CTL3 data is delayed 1 pixel clocks
2=CTL3 data is delayed 2 pixel clocks
3=CTL3 data is delayed 3 pixel clocks
4=CTL3 data is delayed 4 pixel clocks
5=CTL3 data is delayed 5 pixel clocks
6=CTL3 data is delayed 6 pixel clocks
7=CTL3 data is delayed 7 pixel clocks
Set to 1 to invert CTL3 data
0=CTL3 data is normal
1=CTL3 data is inverted
CTL3 data modulation control
0=CTL3 data is not modulated
1=CTL3 data is modulated by bit 0 of 2 bit counter
2=CTL3 data is modulated by bit 1 of 2 bit counter
3=CTL3 data is modulated every time 2 bit counter overflows
Set to 1 to enable CTL3 internal feedback path
Set to 1 to force continuous toggle on CTL3 internal feedback path
Select CTL3 output data
0=Register value
1=Pattern generator output
Description
Determines frequency of reference for power sequencing
Frequency = REF/(PWREQ_REF_DIV+1), REF=1MHz (normally)
Determines frequency of modulated BLON
Frequency = REF/(256*(BL_MOD_REF_DIV+1)), REF=1MHz (nor-
mally)
Description
Number of LVTMA_PWRSEQ_REF pulses to delay from DIGON
enable to SYNCEN (LVTMA transmitter macro) enable during pow-
erup. Must be long enough for bandgap reference and PLL startup (=
reset assertion time + PLL lock time).
Number of LVTMA_PWRSEQ_REF pulses to delay from SYNCEN
enable to BLON enable during powerup
Number of LVTMA_PWRSEQ_REF pulses to delay from BLON dis-
able to SYNCEN disable during power down
Number of LVTMA_PWRSEQ_REF pulses to delay from SYNCEN
disable to DIGON disable during power down
Description
Number of LVTMA_PWRSEQ_REF pulses to delay from completion
of powerdown to powerup
© 2007 Advanced Micro Devices, Inc.
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