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VGA Registers
VGA_SURFACE_HEIGHT_SELECT
display buffer pitch Register
Field Name
VGA_MEMORY_BASE_ADDRESS
VGA Base address Register
Field Name
VGA_DISPBUF1_SURFACE_ADDR
display 1 buffer base address
Field Name
VGA_DISPBUF2_SURFACE_ADDR
display 2 buffer base address
Field Name
VGA_MEM_PAGE_SELECT_EN
VGA_RBBM_LOCK_DISABLE
VGA_SOFT_RESET
VGA_TEST_RESET_CONTROL
VGAHDP control register
M56 Register Reference Manual
2-188
9:8
VGA_MEMORY_BASE_ADDRESS - RW - 32 bits - DISPDEC:0x310
Bits
31:0
VGA_DISPBUF1_SURFACE_ADDR - RW - 32 bits - DISPDEC:0x318
Bits
24:0
VGA_DISPBUF2_SURFACE_ADDR - RW - 32 bits - DISPDEC:0x320
Bits
24:0
VGA_HDP_CONTROL - RW - 32 bits - DISPDEC:0x328
Bits
0
8
16
24
VGA_CACHE_CONTROL - RW - 32 bits - DISPDEC:0x32C
0x0
Selects the height of the display buffer
0=768 lines
1=1024 lines
2=1280 lines
3=1408 lines
Default
0x0
Base address of the 32 Meg area that the VGAHDP and VGAREN-
DER access
NOTE: Bits 0:24 of this field are hardwired to ZERO.
Default
0x0
Base address of display 1 buffer within the 32 Meg defined by
VGA_MEMORY_BASE_ADDRESS
NOTE: Bits 0:19 of this field are hardwired to ZERO.
Default
0x0
Base address of display 2 buffer within the 32 Meg defined by
VGA_MEMORY_BASE_ADDRESS
NOTE: Bits 0:19 of this field are hardwired to ZERO.
Default
0x0
Enables write and read paging
0=Don't use VGA_MEM_WRITE_PAGE_ADDR and
VGA_MEM_READ_PAGE_ADDR registers
1=Use VGA_MEM_WRITE_PAGE_ADDR and
VGA_MEM_READPAGE_ADDR registers
0x0
Disables the lock that holds register writes while the memory pipe is
full
0=The RBBM write requests will be held until the data pipe is idle.
1=The RBBM write requests will not be held.
0x0
Does soft reset for VGA, does not reset the registers
0=VGA running in normal operating mode
1=Soft Reset to VGA
0x0
Not used
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
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