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AMD Geode SC2200 Embedded Processor Manuals
Manuals and User Guides for AMD Geode SC2200 Embedded Processor. We have
1
AMD Geode SC2200 Embedded Processor manual available for free PDF download: Data Book
AMD Geode SC2200 Data Book (429 pages)
Processor
Brand:
AMD
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Table of Contents
3
List of Figures
5
List of Figures
8
List of Tables
9
1 0Overview
13
General Description
13
Video Processor
13
Core Logic
13
Figure 1-1. Block Diagram
13
Features
14
General Features
14
2 0Architecture Overview
17
GX1 Module
17
Memory Controller
17
Table 2-1. SC2200 Memory Controller Register Summary
18
Table 2-2. SC2200 Memory Controller Registers
18
Video Processor Module
22
Core Logic Module
23
Superi/O Module
23
Clock, Timers, and Reset Logic
24
3 0Signal Definitions
25
Figure 3-1. Signal Groups
25
Ball Assignments
27
Strap Options
27
Table 3-1. Signal Definitions Legend
27
Figure 3-2. BGU481 Ball Assignment Diagram
28
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number
29
Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name
39
Strap Options
43
Table 3-4. Strap Options
43
Multiplexing Configuration
44
Table 3-5. Two-Signal/Group Multiplexing
44
Table 3-6. Three-Signal/Group Multiplexing
46
Table 3-7. Four-Signal/Group Multiplexing
47
Signal Descriptions
48
System Interface
48
Memory Interface Signals
50
PCI Bus Interface Signals
53
Table 6-44. DMA
59
Power Management Interface Signals
64
GPIO Interface Signals
66
JTAG Interface Signals
67
4 0General Configuration Block
71
Configuration Block Addresses
71
Table 4-1. General Configuration Block Register Summary
71
Multiplexing, Interrupt Selection, and Base Address Registers
72
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers
72
Watchdog
79
Figure 4-1. WATCHDOG Block Diagram
79
Table 4-3. WATCHDOG Registers
80
High-Resolution Timer
81
High-Resolution Timer Registers
81
Table 4-4. High-Resolution Timer Registers
82
Clock Generators and Plls
83
Figure 4-2. Clock Generation Block Diagram
83
Figure 4-3. Recommended Oscillator External Circuitry
84
Table 4-5. Crystal Oscillator Circuit Components
84
Table 4-6. Core Clock Frequency
85
Table 4-7. Strapped Core Clock Frequency
85
5 0Superi/O Module
89
Figure 5-1. SIO Block Diagram
89
Features
90
Module Architecture
91
Figure 5-2. Detailed SIO Block Diagram
91
Configuration Structure/Access
92
Figure 5-3. Structure of the Standard Configuration Register File
92
Table 5-1. SIO Configuration Options
92
Table 5-2. LDN Assignments
92
Address Decoding
93
Standard Configuration Registers
94
Figure 5-4. Standard Configuration Registers Map
94
Table 5-3. Standard Configuration Registers
95
Table 5-4. SIO Control and Configuration Register Map
97
Power Rail
97
Table 5-5. SIO Control and Configuration Registers
97
Table 5-6. Relevant RTC Configuration Registers
98
Table 5-7. RTC Configuration Registers
99
Table 5-8. Relevant SWC Registers
100
Table 5-9. Relevant IRCP/SP3 Registers
101
Table 5-10. IRCP/SP3 Configuration Register
101
Table 5-11. Relevant Serial Ports 1 and 2 Registers
102
Table 5-12. Serial Ports 1 and 2 Configuration Register
102
Table 5-13. Relevant ACB1 and ACB2 Registers
103
Table 5-14. ACB1 and ACB2 Configuration Register
103
Table 5-15. Relevant Parallel Port Registers
104
Table 5-16. Parallel Port Configuration Register
104
Real-Time Clock (RTC)
105
Bus Interface
105
Figure 5-5. Recommended Oscillator External Circuitry
105
Table 5-17. Crystal Oscillator Circuit Components
105
Figure 5-6. External Oscillator Connections
106
Figure 5-7. Divider Chain Control
106
Figure 5-8. Power Supply Connections
108
Figure 5-9. Typical Battery Configuration
108
Figure 5-11. Typical Battery Current: Normal Operation Mode
108
Table 5-18. System Power States
109
Figure 5-12. Interrupt/Status Timing
110
Table 5-19. RTC Register Map
111
Table 5-20. RTC Registers
111
Table 5-21. Divider Chain Control / Test Selection
114
Table 5-22. Periodic Interrupt Rate Encoding
114
Table 5-23. BCD and Binary Formats
114
Table 5-24. Standard RAM Map
115
Table 5-25. Extended RAM Map
115
System Wakeup Control (SWC)
116
Event Detection
116
Table 5-26. Time Range Limits for CEIR Protocols
116
Table 5-27. Banks 0 and 1 - Common Control and Status Register Map
117
Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map
117
Table 5-29. Banks 0 and 1 - Common Control and Status Registers
118
Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers
119
Access.bus Interface
121
Figure 5-13. Bit Transfer
121
Figure 5-14. Start and Stop Conditions
121
Figure 5-15. Access.bus Data Transaction
122
Figure 5-16. Access.bus Acknowledge Cycle
122
Master Mode
123
Figure 5-17. a Complete Access.bus Data Transaction
123
Table 5-31. ACB Register Map
126
Table 5-32. ACB Registers
126
Legacy Functional Blocks
129
Table 5-33. Parallel Port Register Map for First Level Offset
129
Table 5-34. Parallel Port Register Map for Second Level Offset
129
Table 5-35. Parallel Port Bit Map for First Level Offset
130
Table 5-36. Parallel Port Bit Map for Second Level Offset
130
Figure 5-18. UART Mode Register Bank Architecture
131
Table 5-37. Bank 0 Register Map
131
Table 5-38. Bank Selection Encoding
132
Table 5-39. Bank 1 Register Map
132
Table 5-40. Bank 2 Register Map
132
Table 5-41. Bank 3 Register Map
133
Table 5-42. Bank 0 Bit Map
133
Table 5-43. Bank 1 Bit Map
134
Table 5-44. Bank 2 Bit Map
134
Table 5-45. Bank 3 Bit Map
134
Figure 5-19. IRCP/SP3 Register Bank Architecture
135
Table 5-46. Bank 0 Register Map
135
Table 5-47. Bank Selection Encoding
136
Table 5-48. Bank 1 Register Map
136
Table 5-49. Bank 2 Register Map
136
Table 5-50. Bank 3 Register Map
137
Table 5-51. Bank 4 Register Map
137
Table 5-52. Bank 5 Register Map
137
Table 5-53. Bank 6 Register Map
138
Table 5-54. Bank 7 Register Map
138
Table 5-55. Bank 0 Bit Map
138
Table 5-56. Bank 1 Bit Map
139
Table 5-57. Bank 2 Bit Map
139
Table 5-58. Bank 3 Bit Map
139
Table 5-59. Bank 4 Bit Map
139
Table 5-60. Bank 5 Bit Map
140
Table 5-61. Bank 6 Bit Map
140
Table 5-62. Bank 7 Bit Map
140
6 0Core Logic Module
141
Feature List
141
Module Architecture
142
Figure 6-1. Core Logic Module Block Diagram
142
Ide Controller
144
Register Descriptions
145
Table 6-1. Physical Region Descriptor Format
145
Table 6-2. Ultradma/33 Signal Definitions
146
Universal Serial Bus
147
Figure 6-2. Non-Posted Fast-PCI to ISA Access
148
Figure 6-3. PCI to ISA Cycles with Delayed Transaction Enabled
149
Figure 6-4. ISA DMA Read from PCI Memory
150
Figure 6-5. ISA DMA Write to PCI Memory
150
Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls
151
Figure 6-6. PCI Change to Sub-ISA and Back
152
Figure 6-7. PIT Timer
154
Figure 6-8. PIC Interrupt Controllers
155
Table 6-4. PIC Interrupt Mapping
155
Figure 6-9. PCI and IRQ Interrupt Mapping
156
Keyboard Support
157
Figure 6-10. SMI Generation for NMI
157
Power Management Logic
158
Table 6-5. Wakeup Events Capability
159
Table 6-7. Power Planes Vs. Sleep/Global States
160
Table 6-8. Power Management Events
160
Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example
165
Table 6-9. Device Power Management Programming Summary
166
GPIO Interface
167
Integrated Audio
167
Table 6-10. Bus Masters that Drive Specific Slots of the AC97 Interface
167
Table 6-11. Physical Region Descriptor Format
168
Figure 6-12. PRD Table Example
169
Figure 6-13. AC97 V2.0 Codec Signal Connections
170
Figure 6-14. Audio SMI Tree Example
172
Figure 6-15. Typical Setup
173
Table 6-12. Cycle Types
174
Register Summary
176
Table 6-15. F0BAR0: GPIO Support Registers Summary
179
Table 6-16. F0BAR1: LPC Support Registers Summary
179
Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
180
Table 6-18. F1BAR0: SMI Status Registers Summary
180
Table 6-19. F1BAR1: ACPI Support Registers Summary
181
Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary
182
Table 6-21. F2BAR4: IDE Controller Support Registers Summary
183
Table 6-22. F3: PCI Header Registers for Audio Support Summary
183
Table 6-23. F3BAR0: Audio Support Registers Summary
184
Table 6-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
185
Table 6-25. F5BAR0: I/O Control Support Registers Summary
185
Table 6-26. PCIUSB: USB PCI Configuration Register Summary
186
Table 6-27. USB_BAR: USB Controller Registers Summary
187
Table 6-28. ISA Legacy I/O Register Summary
188
Chipset Register Space
190
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support
190
Table 6-30. F0BAR0+I/O Offset: GPIO Configuration Registers
223
Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers
227
Table 6-32. F1: PCI Header Registers for SMI Status and ACPI Support
235
Table 6-33. F1BAR0+I/O Offset: SMI Status Registers
236
Table 6-34. F1BAR1+I/O Offset: ACPI Support Registers
245
Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration
254
Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers
258
Table 6-37. F3: PCI Header Registers for Audio Configuration
260
Table 6-38. F3Bar0+Memory Offset: Audio Configuration Registers
261
Table 6-39. F5: PCI Header Registers for X-Bus Expansion
275
Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers
278
Table 6-41. PCIUSB: USB PCI Configuration Registers
280
Table 6-42. Usb_Bar+Memory Offset: USB Controller Registers
283
Table 6-43. DMA Channel Control Registers
293
Table 6-45. Programmable Interval Timer Registers
299
Table 6-46. Programmable Interrupt Controller Registers
301
Table 6-47. Keyboard Controller Registers
304
Table 6-48. Real-Time Clock Registers
305
Table 6-49. Miscellaneous Registers
305
7 0Video Processor Module
307
Module Architecture
308
Figure 7-1. Video Processor Block Diagram
308
Functional Description
309
Figure 7-2. NTSC 525 Lines, 60 Hz, Odd Field
310
Figure 7-3. NTSC 525 Lines, 60 Hz, Even Field
310
Figure 7-4. VIP Block Diagram
311
Figure 7-5. Capture Video Mode Bob Example Using One Video Frame Buffer
313
Figure 7-6. Capture Video Mode Weave Example Using Two Video Frame Buffers
314
Figure 7-7. Video Block Diagram
315
Figure 7-8. Horizontal Downscaler Block Diagram
316
Figure 7-9. Linear Interpolation Calculation
317
Figure 7-10. Mixer/Blender Block Diagram
318
Table 7-1. Valid Mixing/Blending Configurations
319
Figure 7-11. Graphics/Video Frame with Alpha Windows
320
Table 7-2. Truth Table for Alpha Blending
321
Figure 7-12. Color Key and Alpha Blending Logic
322
Figure 7-13. DAC Voltage Levels
323
Figure 7-14. TFT Power Sequence
324
Figure 7-15. PLL Block Diagram
325
Register Descriptions
326
Table 7-3. F4: PCI Header Registers for Video Processor Support Summary
326
Table 7-4. F4BAR0: Video Processor Configuration Registers Summary
326
Table 7-5. F4BAR2: VIP Support Registers Summary
328
Table 7-6. F4: PCI Header Registers for Video Processor Support Registers
329
Table 7-7. F4Bar0+Memory Offset: Video Processor Configuration Registers
331
Table 7-8. F4Bar2+Memory Offset: VIP Configuration Registers
345
8 0Debugging and Monitoring
349
Testability (JTAG)
349
Table 8-1. JTAG Mode Instruction Support
349
9 0Electrical Specifications
351
General Specifications
351
Table 9-1. Electro Static Discharge (ESD)
351
Table 9-2. Absolute Maximum Ratings
351
Table 9-3. Operating Conditions
352
Table 9-4. Power Planes of External Interface Signals
353
Table 9-5. System Conditions Used to Measure SC2200 Current During the on State
354
Table 9-6. DC Characteristics for on State
354
Table 9-7. DC Characteristics for Active Idle, Sleep, and off States
355
Table 9-8. Ball Capacitance and Inductance
356
Pull-Up and Pull-Down Resistors
357
DC Characteristics
358
Figure 9-1. Differential Input Sensitivity for Common Mode Range
361
AC Characteristics
363
Figure 9-2. General Drive Level and Measurement Points
363
Memory Controller Interface
364
Figure 9-3. Drive Level and Measurement Points
364
Figure 9-4. Memory Controller Output Valid Timing Diagram
366
Figure 9-5. Read Data in Setup and Hold Timing Diagram
366
Figure 9-6. Video Input Port Timing Diagram
367
Figure 9-7. TFT Timing Diagram
368
Figure 9-8. ACB Signals: Rising Time and Falling Timing Diagram
371
Figure 9-9. ACB Start and Stop Condition Timing Diagram
371
Figure 9-10. ACB Start Condition Timing Diagram
372
Figure 9-11. ACB Data Bit Timing Diagram
372
PCI Bus Interface
373
Figure 9-12. Testing Setup for Slew Rate and Minimum Timing
373
Figure 9-13. V/I Curves for PCI Output Signals
374
Figure 9-14. PCICLK Timing and Measurement Points
375
Figure 9-15. Load Circuits for Maximum Time Measurements
376
Figure 9-16. Output Timing Measurement Conditions
377
Figure 9-17. Input Timing Measurement Conditions
378
Figure 9-18. PCI Reset Timing
378
Figure 9-19. Sub-ISA Read Operation Timing Diagram
381
Figure 9-20. Sub-ISA Write Operation Timing Diagram
382
Figure 9-21. LPC Output Timing Diagram
383
Figure 9-22. LPC Input Timing Diagram
383
Ide Interface
384
Figure 9-23. IDE Reset Timing Diagram
384
Figure 9-24. Register Transfer To/From Device Timing Diagram
386
Figure 9-25. PIO Data Transfer To/From Device Timing Diagram
388
Figure 9-26. Multiword DMA Data Transfer Timing Diagram
390
Figure 9-27. Initiating an Ultradma Data in Burst Timing Diagram
392
Figure 9-28. Sustained Ultradma Data in Burst Timing Diagram
393
Figure 9-29. Host Pausing an Ultradma Data in Burst Timing Diagram
394
Figure 9-30. Device Terminating an Ultradma Data in Burst Timing Diagram
395
Figure 9-31. Host Terminating an Ultradma Data in Burst Timing Diagram
396
Figure 9-32. Initiating an Ultradma Data out Burst Timing Diagram
397
Figure 9-33. Sustained Ultradma Data out Burst Timing Diagram
398
Figure 9-34. Device Pausing an Ultradma Data out Burst Timing Diagram
399
Figure 9-35. Host Terminating an Ultradma Data out Burst Timing Diagram
400
Figure 9-36. Device Terminating an Ultradma Data out Burst Timing Diagram
401
Universal Serial Bus (USB) Interface
402
Figure 9-37. Data Signal Rise and Fall Timing Diagram
404
Figure 9-38. Source Differential Data Jitter Timing Diagram
404
Figure 9-39. EOP Width Timing Diagram
405
Figure 9-40. Receiver Jitter Tolerance Timing Diagram
405
Serial Port (UART)
406
Figure 9-41. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram
406
Figure 9-42. Fast IR (mir and FIR) Timing Diagram
407
Figure 9-43. Standard Parallel Port Typical Data Exchange Timing Diagram
408
Figure 9-44. Enhanced Parallel Port Timing Diagram
409
Figure 9-45. ECP Forward Mode Timing Diagram
410
Figure 9-46. ECP Reverse Mode Timing Diagram
411
Figure 9-47. AC97 Reset Timing Diagram
412
Figure 9-48. AC97 Sync Timing Diagram
412
Figure 9-49. AC97 Clocks Diagram
413
Figure 9-50. AC97 Data Timing Diagram
414
Figure 9-51. AC97 Rise and Fall Timing Diagram
415
Figure 9-52. AC97 Low Power Mode Timing Diagram
416
Figure 9-53. PWRBTN# Trigger and ONCTL# Timing Diagram
417
Figure 9-54. GPWIO and ONCTL# Timing Diagram
417
Figure 9-55. Power-Up Sequencing with PWRBTN# Timing Diagram
418
Figure 9-56. Power-Up Sequencing Without PWRBTN# Timing Diagram
419
JTAG Interface
420
Figure 9-57. TCK Measurement Points and Timing Diagram
420
Figure 9-58. JTAG Test Timing Diagram
421
10 0Package Specifications
423
Thermal Characteristics
423
Figure 10-1. Heatsink Example
424
Physical Dimensions
425
Figure 10-2. BGU481 Package - Top View
425
Figure 10-3. BGU481 Package - Bottom View
426
Appendix A Support Documentation
427
Order Information
427
Data Book Revision History
428
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