AMD M56 Reference Manual page 129

VIPH_DV1_WID
VIPH_DV2_WID
VIPH_DV3_WID
VIPH_PWR_DOWN (R)
VIPH_PWR_DOWN_AK (W)
VIPH_VIPCLK_DIS
VIP Host Port Control
Field Name
VIPH_TIME_UNIT
VIPH_DV0_LAT
VIPH_DV1_LAT
VIPH_DV2_LAT
VIPH_DV3_LAT
Time slice partition
Field Name
VIPH_CH0_CHUNK
VIPH_CH1_CHUNK
VIPH_CH2_CHUNK
VIPH_CH3_CHUNK
VIPH_CH0_ABORT
VIPH_CH1_ABORT
VIPH_CH2_ABORT
VIPH_CH3_ABORT
DMA transfer chunk size and abort control
© 2007 Advanced Micro Devices, Inc.
Proprietary
25 0x0
26 0x0
27 0x0
28 0x0
28 0x0
29 0x0
VIPH_DV_LAT - RW - 32 bits - VIPDEC:0xC44
Bits Default
11:0 0x0
19:16 0x0
23:20 0x0
27:24 0x0
31:28 0x0
VIPH_DMA_CHUNK - RW - 32 bits - VIPDEC:0xC48
Bits Default
3:0 0x0
5:4 0x0
7:6 0x0
9:8 0x0
16 0x0
17 0x0
18 0x0
19 0x0
VIPH1 bus width
0=2-bit vipbus
1=4-bit vipbus
VIPH2 bus width
0=2-bit vipbus
1=4-bit vipbus
VIPH3 bus width
0=2-bit vipbus
1=4-bit vipbus
'1' to wake up PCICLK.
0=Normal
1=STARTUP PCICLK
Clear PWR_DOWN by writing a 1. In order to support PCICLK power
down mode, it is important to clear this bit every time there is an inter-
rupt from any part of VIP
0=Normal
1=Allow the host bus to go back to power down state
'0' will supply VIP clock to slave. '1' will stops VIP clock to save
power.
0=
1=turn off VIPCLK for power saving
Description
Basic time slice
How many time slice port 0 gets
How many time slice port 1 gets
How many time slice port 2 gets
How many time slice port 3 gets
Description
Chunk size between VIP host port and DMA for port 0
Chunk size between VIP host port and DMA for port 1
Chunk size between VIP host port and DMA for port 2
Chunk size between VIP host port and DMA for port 3
Abort DMA operation through port 0
Abort DMA operation through port 1
Abort DMA operation through port 2
Abort DMA operation through port 3
M56 Register Reference Manual
VIP/I2C Registers
2-123