Table of Contents
Advertisement
CRTC Registers
D2CRTC_H_SYNC_B_POL
D2CRTC_COMP_SYNC_B_EN
D2CRTC_H_SYNC_B_CUTOFF
Controls horizontal sync B for CRTC2
Field Name
D2CRTC_V_TOTAL
Defines the vertical dimension of display timing for CRTC2
Field Name
D2CRTC_V_BLANK_START
D2CRTC_V_BLANK_END
Defines the position of the vertical blank region for CRTC2
Field Name
D2CRTC_V_SYNC_A_START
D2CRTC_V_SYNC_A_END
Defines the position of vertical sync A for CRTC2
Field Name
D2CRTC_V_SYNC_A_POL
Controls V SYNC A for CRTC2
M56 Register Reference Manual
2-282
0
16
17
D2CRTC_V_TOTAL - RW - 32 bits - DISPDEC:0x6820
Bits
12:0
D2CRTC_V_BLANK_START_END - RW - 32 bits - DISPDEC:0x6824
Bits
12:0
28:16
D2CRTC_V_SYNC_A - RW - 32 bits - DISPDEC:0x6828
Bits
12:0
28:16
D2CRTC_V_SYNC_A_CNTL - RW - 32 bits - DISPDEC:0x682C
Bits
0
0x0
Polarity of H SYNC B
0 = active high
1 = active low
0x0
Enables composite H SYNC B
0 = disabled
1 = enabled
0x0
Cutoff horizontal sync B at end of horizontal blank region when end of
H SYNC B is beyond horizontal blank
0 = cutoff is enabled
1 = cutoff is disabled
Default
0x0
Vertical total minus one. Sum of vertical active display, top and bot-
tom overscan, front and back porch and vertical sync width.
E.g. for 525 lines set to 524 = 0x20C
Double-buffered with D2MODE_MASTER_UPDATE_LOCK
Default
0x0
Vertical blank start. Determines the position of the first blank line in a
frame. Line 0 is the first line of vertical sync A.
Double-buffered with D2MODE_MASTER_UPDATE_LOCK
0x0
Vertical blank end. Determines the position of the next line after the
last line of vertical blank. The last line of vertical blank is
D2CRTC_V_BLANK_END - 1.
Double-buffered with D2MODE_MASTER_UPDATE_LOCK
Default
0x0
The first line of vertical sync A. In normal cases, it is set to 0. It is set
to non-zero value only when trying to test the higher bits of the verti-
cal counter
0x0
Vertical sync A end. Determines the position of the next line after the
last line of vertical sync A. The last line of vertical sync A is
D2CRTC_V_SYNC_A_END - 1. The first line of vertical sync A is line
0. This register value is exclusive. It should be programmed to a
value one greater than the actual last line of vertical sync A
Double-buffered with D2MODE_MASTER_UPDATE_LOCK
Default
0x0
Polarity of V SYNC A
0 = active high
1 = active low
Double-buffered with D2MODE_MASTER_UPDATE_LOCK
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
Advertisement
Table of Contents
