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2.8
CRTC Registers
Field Name
D1CRTC_H_TOTAL
Defines horizontal dimension of the display timing for CRTC1
Field Name
D1CRTC_H_BLANK_START
D1CRTC_H_BLANK_END
Defines horizontal blank region of the display timing for CRTC1
Field Name
D1CRTC_H_SYNC_A_START
D1CRTC_H_SYNC_A_END
Defines horizontal sync A position for CRTC1
Field Name
D1CRTC_H_SYNC_A_POL
D1CRTC_COMP_SYNC_A_EN
D1CRTC_H_SYNC_A_CUTOFF
Controls the H SYNC A for CRTC1
© 2007 Advanced Micro Devices, Inc.
Proprietary
D1CRTC_H_TOTAL - RW - 32 bits - DISPDEC:0x6000
Bits
12:0
D1CRTC_H_BLANK_START_END - RW - 32 bits - DISPDEC:0x6004
Bits
12:0
28:16
D1CRTC_H_SYNC_A - RW - 32 bits - DISPDEC:0x6008
Bits
12:0
28:16
D1CRTC_H_SYNC_A_CNTL - RW - 32 bits - DISPDEC:0x600C
Bits
0
16
17
Default
0x0
Horizontal total minus one. Sum of display width, overscan left and
right, front and back porch and H sync width.
E.g. for 800 pixels set to 799 = 0x31F
Double-buffered with D1MODE_MASTER_UPDATE_LOCK
Default
0x0
Start of the horizontal blank. The location of the first pixel of horizon-
tal blank, relative to pixel zero. If right overscan border, then blank
starts after border ends.
Double-buffered with D1MODE_MASTER_UPDATE_LOCK
0x0
End of the horizontal blank. The location of the next pixel after the
last pixel of horizontal blank, relative to pixel zero.
Double-buffered with D1MODE_MASTER_UPDATE_LOCK
Default
0x0
First pixel of horizontal sync A.
In normal cases, it is set to 0. It is only set to non-zero value when we
want to test the higher bits of the H counter.
This register should be ignored and set to 0x0 in VGA timing mode.
Hardware does not support odd number value for this register.
0x0
Horizontal sync A end. Determines position of the next pixel after last
pixel of horizontal sync A. The last pixel of horizontal sync A is
D1CRTC_H_SYNC_A_END - 1. The first pixel of horizontal sync A is
pixel 0. It should be programmed to a value one greater than the
actual last pixel of horizontal sync A.
Double-buffered with D1MODE_MASTER_UPDATE_LOCK
Default
0x0
Polarity of H SYNC A
0 = active high
1 = active low
Double-buffered with D1MODE_MASTER_UPDATE_LOCK
0x0
Enables composite H sync A
0 = disabled
1 = enabled
0x0
Cutoff H sync A at end of H BLANK when end of H sync A is beyond
H BLANK
0 = cutoff is enabled
1 = cutoff is disabled
CRTC Registers
Description
Description
Description
Description
M56 Register Reference Manual
2-267
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