Memory Controller Registers - AMD M56 Reference Manual

Memory Controller Registers

2.1 Memory Controller Registers
NOTE: Channels A0, A1, B0 and B1 are also known as Channels A, B, C and D respectively.
Field Name
MC_IND_ADDR
MC_IND_SEQ_RBS_0
MC_IND_SEQ_RBS_1
MC_IND_SEQ_RBS_2
MC_IND_SEQ_RBS_3
MC_IND_AIC_RBS
MC_IND_CITF_ARB0
MC_IND_CITF_ARB1
MC_IND_WR_EN
MC_IND_RD_INV
Within MC_IND_INDEX, there are 16 bits of address, and 7 bits of mask. Each of the 7 bits of mask designates a physically distinct group of reg-
isters (in separate physical tile). One bit each for the four sequencer blocks (SQ), the AC block, MCT and MCB. A write may be done in a broad-
cast fashion, simultaneously programming all registers with the same indirect address in the 7 different blocks. The indirect address space is
semantically non-overlapping, such that writes can typically be done with all mask bits being set to "on". Reads tend to be from single registers, so
only one mask bit is set. If more than one mask bit is set, the resulting return data will be the bitwise logical OR of all matching registers. If the
MC_IND_RD_INV bit is set, with a single read mask, the return data will be bitwise inverted; if the bit is set with more than one mask bit set, the
inverted data will then return the bitwise logical NAND of all matching registers. Thus this "collect" read could be useful for polling status bits with
either a logical and or an or.
Field Name
MC_IND_DATA
This is the Indirect memory controller Data registers – aka the indirect data register
Field Name
MEM_PWRUP_COMPL (R)
MC_IDLE (R)
Status register for memory controller
M56 Register Reference Manual
2-2
MC_IND_INDEX - RW - 32 bits - MCDEC:0x70
Bits Default
15:0 0x0
16 0x0 0=Do not access sequencer+gfx return bus block 0 (channels
A0+A1)
1=Access sequencer+gfx return bus block 0 (channels A0+A1)
17 0x0 0=Do not access sequencer+gfx return bus block 1 (channels
B0+B1)
1=Access sequencer+gfx return bus block 1 (channels B0+B1)
18 0x0
19 0x0
20 0x0
21 0x0
22 0x0
23 0x0
24 0x0
MC_IND_DATA - RW - 32 bits - MCDEC:0x74
Bits Default
31:0 0x0
MC_STATUS - RW - 8 bits - MCIND:0x0
Bits Default
0 0x0
1 0x0 Indicates that there are no pending or in-process requests in the MC
Description
0=Reserved - do not program
1=Reserved - do not program
0=Reserved - do not program
1=Reserved - do not program
0=Do not access aic+cpvf and glb return bus block
1=Access aic+cpvf and glb return bus block
0=Do not access client MCT interface+arbitration block
1=Access client MCT interface+arbitration block
0=Do not access client MCB interface+arbitration block
1=Access client MCB interface+arbitration block
0=Disable write capability (read only)
1=Enable write capability
0=Do not invert data on return bus
1=Invert data on return bus
Description
Description
0=SDRAM Init in Process
1=Ready
0=Not Idle
1=Idle
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