Table of Contents
Advertisement
Table A-18 All Registers Sorted by Name
MC_PT0_CONTEXT4_MULTI_LEVEL_BASE_ADDR
MC_PT0_CONTEXT5_DEFAULT_READ_ADDR
MC_PT0_CONTEXT5_FLAT_BASE_ADDR
MC_PT0_CONTEXT5_FLAT_END_ADDR
MC_PT0_CONTEXT5_FLAT_START_ADDR
MC_PT0_CONTEXT5_MULTI_LEVEL_BASE_ADDR
MC_PT0_CONTEXT6_DEFAULT_READ_ADDR
MC_PT0_CONTEXT6_FLAT_BASE_ADDR
MC_PT0_CONTEXT6_FLAT_END_ADDR
MC_PT0_CONTEXT6_FLAT_START_ADDR
MC_PT0_CONTEXT6_MULTI_LEVEL_BASE_ADDR
MC_PT0_CONTEXT7_DEFAULT_READ_ADDR
MC_PT0_CONTEXT7_FLAT_BASE_ADDR
MC_PT0_CONTEXT7_FLAT_END_ADDR
MC_PT0_CONTEXT7_FLAT_START_ADDR
MC_PT0_CONTEXT7_MULTI_LEVEL_BASE_ADDR
MC_PT0_PROTECTION_FAULT_STATUS
MC_PT0_SURFACE_PROBE_FAULT_STATUS
MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
MC_PT0_SYSTEM_APERTURE_LOW_ADDR
M56 Register Reference Manual
A-88
Register Name
MC_PT0_CONTEXT5_CNTL
MC_PT0_CONTEXT6_CNTL
MC_PT0_CONTEXT7_CNTL
MC_PT0_SURFACE_PROBE
MC_RBS_CZT_HWM
MC_RBS_DYN_CNTL
MC_RBS_MAP
MC_RBS_MISC
MC_RBS_SUN_HWM
MC_RFSH_CNTL
MC_SEQ_A_PAD_CNTL_I0
MC_SEQ_A_PAD_CNTL_I1
MC_SEQ_CAS_TIMING
MC_SEQ_CK_PAD_CNTL_I0
MC_SEQ_CK_PAD_CNTL_I1
MC_SEQ_CMD
MC_SEQ_CMD_PAD_CNTL_I0
MC_SEQ_CMD_PAD_CNTL_I1
MC_SEQ_DQ_PAD_CNTL_I0
MC_SEQ_DQ_PAD_CNTL_I1
(Continued)
Page
2-42
2-34
2-37
2-38
2-41
2-40
2-42
2-34
2-37
2-38
2-41
2-40
2-42
2-35
2-37
2-39
2-41
2-40
2-42
2-36
2-35
2-36
2-35
2-35
2-30
2-161
2-29
2-30
2-30
2-8
2-18
2-18
2-11
2-16
2-16
2-19
2-17
2-17
2-17
2-17
© 2007 Advanced Micro Devices, Inc.
Proprietary
Advertisement
Table of Contents
