Page 1 AMD SB600 Register Reference Manual (Public Version) Technical Reference Manual Rev. 3.03 P/N: 46155_sb600_rrg_pub_3.03 ©2008 Advanced Micro Devices, Inc.
Page 2 AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur.
Page 3: Table Of Contents
2.3.5 ASF SM bus Host Interface Registers....................182 IDE Controller (Device 20, Function 1) ..................186 2.4.1 PCI Configuration Registers.......................186 2.4.2 IDE I/O Registers ..........................195 ©2008 Advanced Micro Devices, Inc. Table of Contents AMD SB600 Register Reference Manual Proprietary Page 3...
Page 4 IOXAPIC Registers........................296 4.5.1 Direct Access Registers ........................296 4.5.2 Indirect Access Registers........................297 Appendix A: AC97 Audio FAQs ................299 Appendix B: Revision History .................. 300 ©2008 Advanced Micro Devices, Inc. List of Figures AMD SB600 Register Reference Manual Proprietary Page 4...
Page 5: Advanced Micro Devices, Inc. List Of Figures Amd Sb600 Register Reference Manual Proprietary
Figure 2 SB600 PCI Internal Devices and Major Function Blocks ................12 Figure 3 PCI Configuration Spaces for OHCI.......................45 Figure 4 SMBus/ACPI PCI Configuration Space Function Block Association ..............96 ©2008 Advanced Micro Devices, Inc. List of Figures AMD SB600 Register Reference Manual Proprietary Page 5...
Page 6 Table 4-5: ExtEvent Pins to Generate SMI# ......................287 Table 4-6: THRMTRIP Pin ............................288 Table 4-7: TALERT# through GPE ..........................288 Table 4-8: TALERT# to generate SMI#........................288 ©2008 Advanced Micro Devices, Inc. List of Tables AMD SB600 Register Reference Manual Proprietary Page 6...
Page 7: Introduction
1 Introduction About this Manual This manual is a register reference guide for the AMD SB600 Southbridge. It integrates the key I/O, communications, and audio features required in a state-of-the-art PC into a single device. It is specifically designed to operate with AMD’s RADEON IGP Xpress family of integrated graphics processor products in both desktop and mobile PCs.
Page 8 Warning: Do not attempt to modify values of registers or bit fields marked "Reserved." Doing so may cause the system to behave in unexpected manners. ©2008 Advanced Micro Devices, Inc. Nomenclature and Conventions AMD SB600 Register Reference Manual Proprietary Page 8...
Page 9: Features Of The Sb600
Features of the SB600 CPU Interface Supports serial interrupt on quiet and Supports both Single and Dual core AMD continuous modes CPUs DMA Controller Desktop: Athlon 64, Athlon 64 FX, Athlon 64 X2, Sempron, Opteron, dual-core Two cascaded 8237 DMA controllers...
Page 10 Provides clock generator and CPU STPCLK# control Timers Support for ASF 8254-compatible timer Microsoft High Precision Event Timer (HPET) ACPI power management timer ©2008 Advanced Micro Devices, Inc. Features of the SB600 AMD SB600 Register Reference Manual Proprietary Page 10...
Page 11: Block Diagrams
Bus 0 DEV 20 Function 3 SPI bus Device ID 438Dh SMBUS /ACPI Bus 0 DEV 20 Function 0 Device ID 4385h Figure 1 SB600 PCI Internal Devices ©2008 Advanced Micro Devices, Inc. Block Diagrams AMD SB600 Register Reference Manual Proprietary Page 11...
Page 12: Figure 2 Sb600 Pci Internal Devices And Major Function Blocks
TEMPDEAD, TEMPCAUT, INIT#, INT# F:A SHUTDOWN,DC_STOP# RESET# SCIOUT, SLP#, CPUSTP#, PCISTP#, STPCLK#, SOFF#, SMI#, SMIACT# Figure 2 SB600 PCI Internal Devices and Major Function Blocks ©2008 Advanced Micro Devices, Inc. Block Diagrams AMD SB600 Register Reference Manual Proprietary Page 12...
Page 13: Register Descriptions: Pci Devices
MSI Control MSI Address MSI Upper Address MSI Data Power Management Capability ID Power Management Capability Power Management Control And Status ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 13...
Page 14 Read Only. Hard-wired to ‘0’ to indicate that fast back to back Enable is only allowed to the same agent. Interrupt Disable Complies with the PCI 2.3 specification. Reserved 15:11 Reserved. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 14...
Page 15 Sub-Class Code. 01h to indicate an IDE Controller. See Note. Class Code 31:24 Class Code. These 8 bits are read only and wired to 01h to indicate a Mass-Storage Controller. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 15...
Page 16 Base Address for Primary IDE Bus CS1. This register is used Address 0000h for native mode only. Base Address 1 is not used in compatibility mode. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 16...
Page 17 Interrupt Pin - R - 8 bits - [PCI_Reg:3Dh] Field Name Bits Default Description Interrupt Pin Hard-wired to 01h. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 17...
Page 18 Watch Dog Counter - RW - 16 bits - [PCI_Reg:46h] Field Name Bits Default Description Watchdog Counter Specifies the timeout retry count for PCI down stream retries. Reserved 15:8 Reserved. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 18...
Page 19 Hard wired to 000b. COLD D1_Support The D1 state is not supported. D2_Support The D2 state is not supported. PME_Support 15:11 Read-Only. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 19...
Page 20 IDP Index. All register accesses to IDP Data are Dword granularity ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 20...
Page 21 Bit 0 Nominal Output 400mv 450mv 500mv 550mv 600mv 650mv 700mv 750mv Note: This applies to all the ASIC Revisions A11 and above. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 21...
Page 22 Note: This applies to all the ASIC Revisions A11 and above. TX pre-emphasis enable Turns on port2 TX pre-emphasis output 1: Enable pre-emphasis 0: Disable pre-emphasis ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 22...
Page 23 Granularity is 15.5us (Count * 15.5 us) The counter will be disabled if the count is programmed to 0x0. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 23...
Page 24: Bar0/Bar2/Bar1/Bar3 Registers (Sata I/O Register For Ide Mode)
1 = IDE -> Memory This bit should not change during Bus Master transfer cycle, even if terminated by Bus Master IDE stop. Reserved Reserved. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 24...
Page 25: Bar5 Registers
0Ch-0Fh Version(VS) 10h-13h Command Completion Coalescing Control(CCC_CTL) 14h-17h Command Completion Coalescing Ports(CCC_PORTS) 18h-1Bh Enclosure Management Location(EM_LOC) 1Ch-1Fh Enclosure Management Control(EM_CTL) 20h-23h ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 25...
Page 26 Multiplier FIS-based switching. When cleared to ‘0’, indicates that the HBA does not support FIS-based switching. AHCI 1.0 and 1.1 HBAs shall have this bit cleared to ‘0’. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 26...
Page 27 (SNotification) register and its associated functionality. When cleared to ‘0’, the HBA does not support the PxSNTF (SNotification) register and its associated functionality. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 27...
Page 28 MC.MSIE = ‘1’ and MC.MME = 0h. In this case, the hardware has been programmed to use single MSI mode, and is not “reverting” to that mode. Reserved 30:3 Reserved. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 28...
Page 29 ‘0’. On transition of this bit from ‘0’ to ‘1’, any updated values for the TV and CC fields shall take effect. Reserved Reserved ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 29...
Page 30 ‘1’ in the Ports Implemented register. An updated value for this field shall take effect within one timer increment (1 millisecond). ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 30...
Page 31: Port Registers (One Set Per Port)
The structure pointed to by this address range is 256 bytes in length. This address must be 256-byte aligned as indicated by bits 07:00 being read only. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 31...
Page 32 Interface Fatal Error Indicates that the HBA encountered an error on the Serial Status (IFS) ATA interface which caused the transfer to stop. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 32...
Page 33 Task File Error Enable When set, GHC.IE is set, and P0S.TFES is set, the HBA shall (TFEE) generate an interrupt. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 33...
Page 34 FR bit in this register to be cleared Reserved Reserved ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 34...
Page 35 ESP is mutually exclusive with the HPCP bit in this register. Reserved 23:22 Reserved ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 35...
Page 36 PxSACT register and PxCI is cleared. If CAP.SALP is cleared to ‘0’ software shall treat this bit as reserved. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 36...
Page 37 ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 37...
Page 38 Device not present or communication not established Generation 1 communication rate negotiated Generation 2 communication rate negotiated All other values reserved. Read Only ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 38...
Page 39 Limit speed negotiation to Generation 1 communication rate Limit speed negotiation to a rate not greater than Generation 2 communication rate All other values reserved ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 39...
Page 40 All other values reserved Select Power 15:12 Read Only Management (SPM) Port Multiplier Port 19:16 Read Only (PMP) Reserved 31:20 Reserved ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 40...
Page 41 Data FIS is received, including reception FIFO overflow, CRC error or 10b8b decoding error. Write 1 to clear these bits. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 41...
Page 42 PhyRdy Change (N): Indicates that the PhyRdy signal changed state. This bit is reflected in the P0IS.PRCS bit. ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 42...
Page 43 This field is reset to default on a HBA Reset, but it is not reset by COMRESET or software reset. Reserved 31:16 Reserved ©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0) AMD SB600 Register Reference Manual Proprietary Page 43...
Page 44: Ochi Usb 1.1 And Ehci Usb 2.0 Controllers
68h – 69h Target Timeout Control MSI Control MSI Address MSI Data HT MSI Support OHCI1/2/3/4 – PCI config ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 44...
Page 45: Figure 3 Pci Configuration Spaces For Ohci
Device / Vendor ID – R - 32 bits - [PCI_Reg : 00h] Field Name Bits Default Description VEND_ID 15:0 1002h Vendor ID ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 45...
Page 46 Hard-wired to 1, indicating 66MHz capable. Reserved Reserved Fast Back-to- Hard-wired to 1, indicating Fast Back-to-Back capable. Back Capable ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 46...
Page 47 32-bit memory space; i.e., lower 4 GB of the main memory of the PC host. Read Only. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 47...
Page 48 Config Timers / MSI Disable (OHCI0 only) – RW - 16 bits - [PCI_Reg : 40h] Field Name Bits Default Description TRDY Timer Target Ready timer to timeout non-responding target. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 48...
Page 49 Port-4. There are 10 OverCurrent pins (USB_OC0 ~ USB_OC9), any value greater than 0x9h will disable the OverCurrent function for port-4. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 49...
Page 50 Writing this bit to a one enables the respective port to be sensitive to over-current conditions as wake-up events when it is owned by OHCI. Reserved 15:10 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 50...
Page 51: Ohci Operational Registers (Mem_Reg)
0. Register Name Offset Address HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 51...
Page 52 SOF. HC must check this bit before it starts processing the list. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 52...
Page 53 ESET reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 53...
Page 54 Root Hub and no subsequent reset signaling should be asserted to its downstream ports. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 54...
Page 55 HcInterruptStatus has already been set. This is used by HCD to monitor any persistent scheduling problems. Reserved 31:18 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 55...
Page 56 1 - Enable interrupt generation due to HcDoneHead Writeback. 0 - Ignore 1 - Enable interrupt generation due to Start of Frame. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 56...
Page 57 Bits Default Description Reserved Reserved HCCA 31:8 000000h This is the base address of the Host Controller Communication Area ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 57...
Page 58 HCCA during the initialization of HC. HcBulkCurrentED - 32 bits - [MEM_Reg : 2Ch] Field Name Bits Default Description Reserved Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 58...
Page 59 The field value is calculated by the HCD. FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 59...
Page 60 FrameRemaining  t his field. The value is calculated by HCD with the consideration of transmission and setup overhead. Reserved 31:12 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 60...
Page 61 It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 61...
Page 62 1 = ConnectStatusChange is a remote wakeup event. (Write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoveWakeupEnable. Writing a '0' has no effect. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 62...
Page 63 CurrentConnectStatus is not affected by any write. Note: This bit is always read ‘1b’ when the attached device is non-removable (DeviceRemoveable[NDP]). ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 63...
Page 64 The HCD writes a ‘1’ to initiate a resume. Writing a ‘0’ has no effect. A resume is initiated only if PortSuspendStatus is set. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 64...
Page 65 The HCD clears the PortPowerStatus bit by writing a ‘1’ to this bit. Writing a ‘0’ has no effect. Reserved 15:10 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 65...
Page 66: Usb Legacy Keyboard Operation
PS/2-compatible keyboard and/or mouse interface. To minimize hardware impact, the Host Controller accesses a USB keyboard and/or mouse using the ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 66...
Page 67: System Requirements
OS for any purpose. In addition, this memory must be accessible by the host CPU while the host CPU is in SMM. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 67...
Page 68: Programming Interface
HceStatus with no other side effect. HceInput OUT to port 64h will set InputFull to 0 and CmdData in HceStatus to 1. HceInput Register ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 68...
Page 69: Table 2-4 Hceinput Registers
Host Controller’s operational register space. Accessing this register through its memory address produces no side effects. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 69...
Page 70: Ehci Registers (Device 19, Function 5)
PCI Configuration Registers Registers Name Offset Address Device / Vendor ID Command Status Revision ID / Class Code Miscellaneous ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 70...
Page 71 A value of 0 enables the assertion of the device/function’s INTx# signal. A value of 1 disables the assertion of the device/function’s INTx# signal. Reserved 15:11 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 71...
Page 72 This field specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 72...
Page 73 Capability Pointer – R - 8 bits - [PCI_Reg : 34h] Field Name Bits Default Description Capability Pointer Address of the 1 element of capability link. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 73...
Page 74 23:21 Disable Async QH Cache Set to 1 to disable async QH/QTD cache during IN xfer. on IN xfer ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 74...
Page 75 When this bit is a “0”, it indicates that no PCI clock is required for the function to generate PME#. Reserved Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 75...
Page 76 This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. Reserved 21:16 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 76...
Page 77 BAR indicated by BAR#. This offset is required to be DWORD aligned and therefore bits 16 and 17 are always zero. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 77...
Page 78 (above) in this register is a one, the host controller will issue an SMI immediately. Reserved. 12:6 These bits are reserved and must be set to zero. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 78...
Page 79: Host Controller Capability Registers (Mem_Reg)
Host Controller Interface Version – HCIVERSION Structural Parameters – HCSPARAMS Capability Parameters - HCCPARMAS Companion Port Route Description – HCSP-PORTROUTE ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 79...
Page 80 When this bit is a one, the port status and control registers include a read/writeable field for controlling the state of the port indicator. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 80...
Page 81 PCI header defined for this class of device. Reserved 31:16 These bits are reserved and should be set to zero. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 81...
Page 82: Host Controller Operational Registers (Eor_Reg)
Halted state (i.e. HCHalted in the USBSTS register is a one). Doing so will yield undefined results. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 82...
Page 83 Light Host Controller Reset has not yet completed. If not implemented a read of this field will always return a zero. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 83...
Page 84 If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 84...
Page 85 Asynchronous Schedule is either enabled (1) or disabled (0). [Read-only] Reserved 31:16 These bits are reserved and should be set to zero. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 85...
Page 86 Base Address 31:12 000h These bits correspond to memory address signals [31:12], respectively. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 86...
Page 87 0 = This port does not have an over-current condition. This bit will automatically transition from a one to a zero when the over current condition is removed. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 87...
Page 88 Port enabled bit is a zero) the results are undefined. This field is zero if Port Power is zero. ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 88...
Page 89 PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port). [Read-write or Read-only] ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 89...
Page 90 The value represents multiple of 8 bytes – 10h means 128 bytes. The smallest acceptable value is 08h (64 bytes). Reserved 31:24 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 90...
Page 91 0010 – Port2 …… 1001 – Port9 1010 ~ 1110 : Reserved , no effect 1111 – Common block ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 91...
Page 92: Usb2.0 Debug Port Registers
USB2.0 Debug Port Registers This block of registers is memory-mapped. The base offset, Dbase, is directly defined in DBUG_PRT ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 92...
Page 93 1 to this bit will clear it. Writing a 0 to this bit has no effect. Reserved 27:17 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 93...
Page 94 NAKs the request). This field is valid when the controller sets the Done bit. Reset default = undefined. Reserved 31:24 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 94...
Page 95 7-bit field that identifies the USB device address used by the controller for all Token PID generation. Reserved 31:15 Reserved ©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers AMD SB600 Register Reference Manual Proprietary Page 95...
Page 96: Smbus Module And Acpi Block (Device 20, Function 0)
8250 Timer Eenable PCI_Reg: PCI-SPCI clock ratio PCI_Reg: B0/E0 h AD:AC Figure 4 SMBus/ACPI PCI Configuration Space Function Block Association ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 96...
Page 97: Pci Configuration Registers And Extended Registers
MiscEnable AzIntMap Features Enable SeriallrqControl RTCProtect USB Reset TestMode IoApic_Conf IoAddrEnable GPIO_69_68_66_65_Cntrl GPIO_3_to_0_Cntrl GPIO_32_31_14_13_Cntrl Smbus Base Address IDE_GPIO_Cntrl ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 97...
Page 98 VGA pallette registers. This does not apply to this module and so it is always 0. [Read-only] ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 98...
Page 99 This bit is set by device whenever it detects a parity error, even if parity error handling is disabled. PCI device status register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 99...
Page 100 Base Address 2- R - 32 bits - [PCI_Reg: 18h] Field Name Bits Default Description Base Address 2 31:0 0000_000 Not used and is hardcoded to 0. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 100...
Page 101 B0/00h For K8 system default value is B0h; for P4 system default value is 00h. Capability Pointer register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 101...
Page 102 MiscfuncEnable When set, this module will decode cycles to IO C50, C51, C52: GPM controls. Reserved MiscFunction register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 102...
Page 103 The SB600 does not have any ISA master, because the bus is internal; however, it may affect the DMA transfers with the LPC module. Software should set all these bits to 1's. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 103...
Page 104 0: Output = GPIO_Out 1: Output = tristate GPIO_Status 11:8 GPIO input status for each of the GPIO port Reserved 15:12 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 104...
Page 105 If SmartVoltEnable is set and this bit is also set, the SmartPower function will only assert SmartVolt if CPU is in C3 state SmartPowerControl1A register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 105...
Page 106 1; otherwise K8 INTR NMI Message Type is controlled by MT3_Auto. Recommended method is to use MT3_Auto bit.. In AMD K8 system, all interrupts are sent to CPU via messages. In MP base (such as Linux), the message may need to be in certain format.
Page 107 High Precision Event Timer (also called Multimedia Timer) interrupt enable Ext_A20En Enable external Ga20In input. When set to 1, GEVENT[0] is used as Ga20In input ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 107...
Page 108 Set to 1 to enable EHCI OHCI_0_enable Set to 1 to enable OHCI_0 OHCI_1_enable Set to 1 to enable OHCI_1 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 108...
Page 109 Forces USB PHY PLL into power down mode. Down Force USB Port PHY Forces USB PHY reset. Reset USB Reset register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 109...
Page 110 [7:4] are enabled Bit[0] for GPIO65/BMREQ# Bit[1] for GPIO66/LLB# Bit[2] for GPIO68/LDRQ1# Bit[3] for GPIO69/RTC_IRQ# ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 110...
Page 111 0 = Memory Reserved 000b SmBusBaseAd 31:4 0000000h SMBus Base Address Smbus Base Address register (also accessible through 10h) ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 111...
Page 112 Amount of “idle” time (in 2us increment) the SmartPower2 function should wait before it should assert SmartVolt 2 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 112...
Page 113 0: GPIO disabled 1: GPIO enabled Bit[13] [15] no effect Use PM_Reg: 60h bit [2] to configure GPIO48/FANOUT1. GPIO_48_47_46_37_Cntrl register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 113...
Page 114 SATA power saving enable Reserved HiddenMsiEnable Setting this bit will make PCI_Reg:B0h, bit 16 to show up as 1. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 114...
Page 115 (OHCI2 & OHCI4) UsbInt3 interrupt mapping to PCI interrupt UsbInt4Map 13:11 011b (EHCI) UsbInt4 interrupt mapping to PCI interrupt ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 115...
Page 116 Approximately 44% of the P and N transistors are enabled 000b Approximately 33% of the P and N transistors are enabled ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 116...
Page 117 SMBus Slave Address for shadow port 1 This value specifies the address used to match against incoming I2C addresses for Shadow port 1. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 117...
Page 118 Set to 1 by MWAIT with addr[19:18] = Mwait_physical_ID[1:0] and addr[17:16] = Mwait_logical_ID[1:0]. Cleared by ADS_after_MWAIT with the same addr[19:16]. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 118...
Page 119 ExtendedDataPort- RW - 32 bits - [PCI_Reg: FCh] Field Name Bits Default Description ExtendedDataPort 31:0 Data port for the extended register block ExtendedDataPort register. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 119...
Page 120: Extended Registers
SpdifGpioIn When AC_SPDIF is configured as GPIO, this bit returns the GPIO input status. Reserved 31:29 AudioPortConfig register. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 120...
Page 121 When ACZ_SDIN 3 is configured as GPIO, this bit represents the output value if the output is enabled. 1 – High 0 – Low ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 121...
Page 122 1 – High 0 – Low Reserved 31:29 AudioGpioControl register. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 122...
Page 123: Smbus Registers
1 to it. AlertStatus This bit is set by hardware to indicate SMBALERT_ signal. This function is not supported. [Read-only] ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 123...
Page 124 Description SMBusBlockData This register is used to transfer data into or out of the block data storage array. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 124...
Page 125 This register controls the frequency on the SMBUS. The formula to calculate the frequency is: Frequency = 66Mhz/(SmBusTiming * 4) ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 125...
Page 126: Legacy Isa And Acpi Controller
Dma_Page_Reserved3 Dma_PageCh0 Dma_Page_Reserved4 Dma_PageCh6 Dma_PageCh7 Dma_PageCh5 Dma_Page_Reserved5 Dma_Page_Reserved6 Dma_Page_Reserved7 Dma_Refresh FastInit IntrCntrl2Reg1 IntrCntrl2Reg2 Dma2_Ch4Addr Dma2_Ch4Cnt Dma2_Ch5Addr Dma2_Ch5Cnt Dma2_Ch6Addr ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 126...
Page 127 Field Name Bits Default Description Dma_Ch 3 15:0 0000h DMA1 Ch3 Base and Current Address Dma_Ch 3 register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 127...
Page 128 IntrCntrl1Reg1- RW – 8 bits - [IO_Reg: 20h] Field Name Bits Default Description IntrCntrl1Reg1 IRQ0 – IRQ7: Read IRR, ISR Write ICW1, OCW2, OCW3 IntrCntrl1Reg1register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 128...
Page 129 61H. It is clocked by OSC/12 (1.19318MHz) and directly drives the output SPKR that goes to a speaker. TimerCh2 register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 129...
Page 130 Field Name Bits Default Description RTC Data Port This is used with either internal RTC or external RTC ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 130...
Page 131 Dma_PageCh0 - RW – 8 bits - [IO_Reg: 87h] Field Name Bits Default Description Dma_PageCh0 DMA2 ch 0 page register Dma_PageCh0 register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 131...
Page 132 0. A20EnB A20Enable Bar bit; if set to 1, A20M is disabled. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 132...
Page 133 Dma2_Ch7Addr - RW – 8 bits - [IO_Reg: CCh] Field Name Bits Default Description Dma2_Ch7Addr DMA2 Ch5 Base and Current Address Dma2_Ch7Addr register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 133...
Page 134 0 – Cold 1 – Warm, this bit is set when any value is written to this register; ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 134...
Page 135 8h – Ac97 modem 9h – INTE# Ah – INTF# Bh – INTG# Ch – INTH# Pci_Intr_Index register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 135...
Page 136 If CMIndex.13h[7:6]= 01, then this is the output enable for GPM[7:0], 0=enable, 1=tristate If CMIndex.13h[7:6]=10, then this is the output state control (providing enable is turned on) ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 136...
Page 137: Client Management Registers (Accessed Through C50H And C51H)
2.3.3.1.2 Client Management Registers (Accessed through C50h and C51h) Register Name Offset Address IdRegister TempStatus TempInterrupt I2Ccontrol Index13 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 137...
Page 138 Placebo bit, has no function but may be used for software status GpmPortSel 00-Read port 01-Output enable 10-Output port Index13 misc control register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 138...
Page 139: System Reset Register (Io Cf9)
ProgramIo2RangeHi ProgramIo3RangeLo ProgramIo3RangeHi ProgramIoEnable IOMonitorStatus InactiveTmrEventEnable4 AcpiPm1EvtBlkLo AcpiPm1EvtBlkHi AcpiPm1CntBlkLo AcpiPm1CntBlkHi AcpiPmTmrBlkLo AcpiPmTmrBlkHi CpuControlLo CpuControlHi AcpiGpe0BlkLo AcpiGpe0BlkHi AcpiSmiCmdLo AcpiSmiCmdHi ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 139...
Page 140 SwitchGHI_Time UsbPMControl MiscEnable66 MiscEnable67 MiscEnable68 WatchDogTimerControl WatchDogTimerBase0 WatchDogTimerBase1 WatchDogTimerBase2 WatchDogTimerBase3 S_LdtStartTime EnhanceOption C4Control PopUpEndTime PwrFailShadow Tpreset1b SOS3ToS5Enable0 SOS3ToS5Enable1 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 140...
Page 141 08,09, and 0A. Timer2ExpEn Set to 1 to enable SMI# when PM_TIMER2 expires. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 141...
Page 142 SmiWakeUpEventStatus2 - RW – 8 bits - [PM_Reg: 06h] Field Name Bits Default Description SmiWakeUpEventStatus2 Set to 1 to identify IRQ[7:0] activity as source of SMI#. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 142...
Page 143 6 bit-timer; Initial/reload value for 6 bit decrementing counter. Count range from 1 minute to 64 minutes with 4 second accuracy. Reserved ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 143...
Page 144 1: Rtc clock running 0: Bad Rtc clock. RTC battery may not be present NbThermStatus NB thermal event status ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 144...
Page 145 PmTmr2CurValue - R – 8 bits - [PM_Reg: 13h] Field Name Bits Default Description PmTmr2CurValue PmTmr2 current value PmTmr2CurValue register. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 145...
Page 146 SMI# when the address is accessed. Bit 7 corresponds to Addr[7] and bit 4 to Addr[4]. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 146...
Page 147 MIDI status bit; write 1’b1 to clear the status bit AudioMSSMonitorStatus Audio/MSS status bit; write 1’b1 to clear the status bit ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 147...
Page 148 These bits define the most significant byte of the 16 bit I/O base address. Bit 0 corresponds to Addr[8] and bit 7 corresponds to Addr[15]. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 148...
Page 149 These bits define the most significant byte of the 16 bit I/O base address. Bit 0 corresponds to Addr[8] and bit 7 corresponds to Addr[15]. AcpiGpe0BlkHi register. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 149...
Page 150 01 GEVENT to generate SMI# 10 GEVENT to generate SMI# followed by SCI 11 GEVENT to generate IRQ13 GEvtConfig1 register. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 150...
Page 151 01 GPM8 to generate SMI# 10 GPM8 to generate SMI# followed by SCI 11 GPM8 to generate IRQ13 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 151...
Page 152 01 SataSci to generate SMI# 10 SataSci to generate SMI# followed by SCI 11 SataSci to generate IRQ13 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 152...
Page 153 0 – Falling edge trigger Gpio2LevelConfig Gpio[2] input level configuration 1 – Rising edge trigger 0 – Falling edge trigger ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 153...
Page 154 01 UsbPme to generate SMI# 10 UsbPme to generate SMI# followed by SCI 11 UsbPme to generate IRQ13 ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 154...
Page 155 Bits Default Description AD_Pull_UpB This register controls integrated pull-up for AD[31:24] respectively. 0: Enable 1: Disable AD_Pull_UpB register. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 155...
Page 156 Timing parameter used for S* -> S0 state transitions. This register determines the CPU_STP# deassertion delay in 8µs increment with 8us uncertainty. Reserved ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 156...
Page 157 Not write and always read 0) SoftPciRst register Reserved – 8 bits - [PM_Reg: 56h] Field Name Bits Default Description Reserved Reserved ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 157...
Page 158 This bit indicates the SMI# status of PCIeHotPlug if it is configured to generate SMI# followed by SCI SmiSciSts1 register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 158...
Page 159 4 CPUs are in mwait state if this bit is set to 1. C2 or C3 is determined by ARB_DIS = 0 or 1. Reserved 000b ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 159...
Page 160 Reserved IsAmd Set to enable NB/SB handshake during IOAPIC interrupt for AMD K6 or K7 class; Clear for other CPU. PCI_Active_enable BIOS should set this bit in order to monitor BM_STS pin from NB (the pin is called BMREQ# on SB) and bus mastering from the SB itself.
Page 161 C State enable; must be set in order to exercise C state Reserved BypassPwrGoodEn If asserted, Southbridge will not wait for deassertion of PWRGOOD to monitor for wakeup event ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 161...
Page 162 WatchDogTimerBase1 – RW – 8 bits – [PM_Reg:6Dh] Field Name Bits Default Description WatchDogTimerBase1 WatchDogTimer Base address [15:8] WatchDogTimerBase1 register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 162...
Page 163 3’b000: 0ns 3'b001: 140ns 3'b010: 210ns 3'b011: 280ns 3'b110: 350ns 3'b111: 420ns 3'b100: 490ns 3'b101: 560ns EnhanceOption register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 163...
Page 164 S5 region. For S4/S5 wake up, this bit must be set in before the corresponding pin can be used Bit [7:0]: GEVENT#[7:0] 1: Enable 0: Disable ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 164...
Page 165 Bit [6]: S5ResetOverride Bit [7]: Enable bit to pass PCI config gevent1_en* bits 1: Enable 0: Disable S0S3ToS5Enable3 register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 165...
Page 166 System management action field for C3 STPCLK message Reserved VFSMAF 010b System management action field for VFID STPCLK message Reserved ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 166...
Page 167 ThermThrotCntl – RW – 8 bits – [PM_Reg:86h] Field Name Bits Default Description Therm2SecDelay Enable 2 second delay for thermal clock throttle ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 167...
Page 168 011: 8µs 100: 16µs 101: 32µs 110: 64µs 111: 128µs StutterMode Set to 1 to enable stutter mode ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 168...
Page 169 AllowLdtStop and cause the C state machine to pop-up to C2. This bit is only valid under K8 CPU configuration. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 169...
Page 170 GPM98IN – RW – 8 bits – [PM_Reg:96h] Field Name Bits Default Description GPM98IN GPM[9:8] input status Reserved GPM98IN register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 170...
Page 171 0000h This register defines the 16 bit IO address for the K8 C1e support. In AMD K8 dual core system, when both CPUs have entered the C1e state, it will broadcast an IO cycle. BIOS can program CPU with this address for such function. When SB receives this IO cycle, it can automatically sequence to C2 or C3 depending on PMIO9Ah, bits [1:0].
Page 172 16 bit I/O range base address. Bit 7 corresponds to Addr[15] and bit 0 to Addr[8]. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 172...
Page 173 Description ProgramIo4Enable Enables IO monitoring for ProgramIO4 (defined by index A0, A1). 1 = On 0 = Off ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 173...
Page 174 The value shows the amount of time the CPU spends in C2. Each increment represents approximately 0.39% (1/256). This register is updated by HW automatically every second C2Count register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 174...
Page 175 Bit [4] = 1 means the SMI source is coming from SCI Bit [5] = 1 means the SMI source is coming from ACPI_GEVENT_STATUS Reserved SmiIndicator2 register ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 175...
Page 176: Acpi Registers
If this bit is set, SCI is generated whenever PwrBtnStatus is true. Reserved RtcEn RTC enable. If this bit is set, SCI is generated whenever RtcStatus is true. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 176...
Page 177 110b: 75% 111b: 87.5% ThtEn This bit enables clock throttling as set in the ClkValue. Reserved 31:5 0000000h ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 177...
Page 178 This bit indicates the status of GPM[4] to SCI/Wakeup GPM5Status This bit indicates the status of GPM[5] to SCI/Wakeup ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 178...
Page 179 SmiCmdStatus - RW - 8 bits – [SmiCmdBlk: 01h] Field Name Bits Default Description SmiCmdStatus Used by BIOS and OS ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 179...
Page 180 Field Name Bits Default Description This register is located at the base address defined by AcpiSmiCmd + offset 1. ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 180...
Page 181: Watchdogtimer Registers
(WDRT). The maximum value is defined in the Max Count field in the WDRT. Reading this register returns in the current counter value. Reserved 31:16 0000h ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 181...
Page 182: Asf Sm Bus Host Interface Registers
Start 0: Always read 0 on reads 1: Writing 1 to initiate the command ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 182...
Page 183 Power up has happened. from ASF RemotePowerDown Power down has happened from ASF RemoteReset Reset has happened from ASF ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 183...
Page 184 1: No SP when turn to read Reserved SuspendSlave Write 1 to Suspend (stop) ASF Slave state machine ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 184...
Page 185 ASF table if the system supports ASF function. Control command Control data value Reset PowerUp PowerDown PowerCycle SensorPolling ©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0) AMD SB600 Register Reference Manual Proprietary Page 185...
Page 186: Ide Controller (Device 20, Function 1)
This register holds a unique 16-bit value assigned to a device, and combined with the vendor ID it, identifies any PCI device. ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 186...
Page 187 Data Parity reported – Set to 1 if the IDE host controller detects PERR- asserted while acting as PCI master (whether PERR- was driven by IDE host controller or not.) ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 187...
Page 188 If the value is 10 that means the cache line size is 16 DW (64 byte). Cache Line Size Register: This register specifies cache line size and the default value is 00. ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 188...
Page 189 Base Address for Secondary IDE Bus CS0. This Base Address used for native mode only. Base Address 2 is not used in compatibility mode. ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 189...
Page 190 Interrupt Line Register: This register identifies which of the system interrupt controllers the device interrupt pin is connected to. The value of this register is used by device drivers. ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 190...
Page 191 15:12 Master DMA Command width for Primary IDE bus Master Command Width DMA device. Reserved 31:16 Reserved. Always read as 0’s ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 191...
Page 192 Transaction is complete, but internal buffer has some data. Status This bit will be cleared by resetting the DMA start bit. Reserved Reserved. Always read as 0’s. ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 192...
Page 193 Reserved Reserved. Always wired as 0’s. PCI Error Control Register: This register specifies DMA parity bit errors. ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 193...
Page 194 MSI Interrupt Weight MSI programmable interrupt weight. Reserved Reserved. Always wired as 0’s. IDE MSI Programmable Weight Register: This register specifies MSI weight. ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 194...
Page 195: Ide I/O Registers
Primary – Base + 00h Register Name Offset Address [Primary] Bus-master IDE Command 00h/08h Bus-master IDE Status 02h/0Ah Bus-master IDE Command 04h/0Ch ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 195...
Page 196: Table 2-8 Ide Device Registers Mapping
Native Mode (Offset) Read Function Write Function IDE Command Block Registers Primary Base Address 0 + 0 Data (16 bit) Data (16 bit) ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 196...
Page 197 Base Address 0 + 7 Status Command IDE Control Block Registers Primary Base Address 1 + 2 Alternate Status Device Control ©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1) AMD SB600 Register Reference Manual Proprietary Page 197...
Page 198: Ac '97 Controller Functional Descriptions
UnMask Latency Timer Expiration IMPORTANT: The driver is required to check revision ID to enable functions appropriately. AMD’s AC’97 controller will be backward compatible to previous revisions. For example, revision 01 will have everything the same as revision 00, plus the enhancement...
Page 199 Status Register: The PCI specification defines this register to record status information for PCI related events. This is a read/write register. However, writes can only reset bits. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 199...
Page 200 Always 0; meaning that it can be located anywhere in 32 bit address space. Prefetchable Always 0; meaning that it is not prefetchable. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 200...
Page 201 Hard-wired to 0 to indicate the bus master has no stringent requirement as to how often the device needs access to the PCI bus. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 201...
Page 202 MSI Program Weight- RW – 8 bits – [PCI_Reg: 4Ch] Field Name Bits Default Description Program Weight This register specifies the programmable priority of audio device’s message signaled interrupt request. Reserved ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 202...
Page 203: Audio Memory Mapped Registers
SPDIF status bits reg2 SPDIF status bits reg3 SPDIF status bits reg4 SPDIF status bits reg5 SPDIF status bits reg6 Audio Phy Semaphore ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 203...
Page 204 Enable new frame start interrupt Set Bus Busy Audio Audio is running (write only). Set/cleared by software. Audio gpio interrupt en Enable audio GPIO interrupt ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 204...
Page 205 0 - Data from memory is transferred in regular way - one DWORD , one data. Loop back enable Enable loop-back mode. The SDATA_OUT connected directly to the SDATA_IN ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 205...
Page 206 Physical address from AC'97 Codec. Input Phy data 31:16 0000h Input Physical data from AC'97 Codec. Input Phy address and data Register ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 206...
Page 207 DMA DT next 31:0 0000_0 Pointer to the next DT for the input DMA 000h Input DMA DT Next Pointer Register: ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 207...
Page 208 DMA DT current 31:0 0000_0 Pointer to the currently accessing memory address for the Output 000h DMA. Output DMA DT Current Pointer Register: ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 208...
Page 209 Default Description SPDIF DT next 31:0 0000_0 Pointer to the next DT for the SPDIF channel. 000h SPDIF channel Next Pointer Register: ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 209...
Page 210 Writing to this bit will flush spdif output DMA fifo, i.e., the fifo indexes and Used/Free counts will be reset. Reading this bit returns 0 Reserved 31:3 0000_0 000h Audio Fifo Flush Register: ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 210...
Page 211 SPDIF Status bits 31:0 0000_0 Same definition as reg0x90. 000h Bits 0~31 in this register correspond to frame 160~191 on spdif bus. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 211...
Page 212 Note: The driver can check Mem_reg 0x10[8] which indicates a PHY read access completion. For writing to PHY, the driver can clear the semaphore bit after the write command. Reserved ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 212...
Page 213: Modem Registers (Device 20, Function 6)
MSI Program Weight IMPORTANT: The driver is required to check revision ID to enable functions appropriately. AMD AC’97 controller will be backward compatible to previous revisions. E.g., Revision 01 will have everything the same as revision 00, plus the enhancement...
Page 214 Revision ID Class Code 31:8 070300h Class Code. Revision ID Register: This read only register contains the device’s revision information and generic function. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 214...
Page 215 This register can only be programmed if index 50h, bit [1] is set. The purpose of this dual address mapping is for diagnostics; not for OS usage ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 215...
Page 216 1 - Function is enabled to use MSI. Multiple Message Hardwired to 0 to indicate the device would like 1 message Capable allocated to it. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 216...
Page 217 When set, bits [13:8] of base 0 (offset 10h) becomes unwritable. This is to cause OS to allocate wider memory map for ac97. Reserved 31:4 0000_0 ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 217...
Page 218: Modem Memory Mapped Registers
Output DMA3 status bit - set to "1" after finishing DT (if reg0x04[1]=1 and reg0x08[5]=1) Phy Data Incoming Got OR’ed Phy register address and data from Codecs ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 218...
Page 219 Enables receiving of modem data from AC link. Modem send out through Enables sending of modem data to slot 5 on AC link DMA1 enable using out DMA1 ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 219...
Page 220 1 – Assert AC link’s SYNC asynchronous to BIT_CLK AC97 Reset# 1 – De-assert AC link’s RESET# asynchronous to BIT_CLK 0 – Assert AC link’s RESET# asynchronous to BIT_CLK ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 220...
Page 221 Even if a bit in this field being 0 indicates a slot is allowed, the controller further looks at reg0x34[9:0] to finally decide whether the slot is enabled. Reserved 31:10 000000h SLOTREQ Register: ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 221...
Page 222 Input DMA DT Size & FIFO info Register: Size of data associated with DT for input channels and number of FIFO entries free and used for the input channels. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 222...
Page 223 DMA1 DT current 31:0 0000_0000h Pointer to the currently accessing memory address for the Output DMA1. Output DMA1 DT Current Pointer Register: ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 223...
Page 224 Number of filled FIFO entries of Output DMA1 (FIFO size 6). out DMA2 Used Number of filled FIFO entries of Output DAM2 (FIFO size 6). ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 224...
Page 225 Writing to this bit flushes modem output DMA2 fifo, i.e., the indexes and Used/Free counts are reset. Reading this bit returns 0. ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 225...
Page 226 Note: The driver can check Mem_reg 0x10[8] which indicates a PHY read access completion. For writing to PHY, the driver can clear the semaphore bit after the write command. Reserved ©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions AMD SB600 Register Reference Manual Proprietary Page 226...
Page 227: Hd Audio Controllers Registers
Vendor ID – R – 16 bits – [PCI_Reg: 00h] Field Name Bits Default Description Vendor ID 15:0 1002h Identifies the vendor as AMD. Device ID – RW – 16 bits – [PCI_Reg: 02h] Field Name Bits Default Description Device ID 15:0 4383h Identifies this device as the HD Audio Controller.
Page 228 Default Description Cache Line Size This field is implemented as a read/write field for legacy compatibility purposes only and has no functional impact. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 228...
Page 229 Capabilities Pointer – R – 8 bits – [PCI_Reg: 34h] Field Name Bits Default Description Capabilities Pointer This register indicates the offset for the capability pointer ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 229...
Page 230 Capability ID Hardwired to 01h. Indicates PCI Power Management Capability. Next Capability Pointer 15:8 Hardwired to 60h. Next capability is at offset 60h ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 230...
Page 231 Hardwired to “0”. Indicates support for one message only. 64 Bit Address Capability Hardwired to “1”. Indicates the ability to generate 64-bit message address. Reserved 15:8 Reserved ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 231...
Page 232: Hd Audio Controller Memory Mapped Registers
RIRB Lower Base Address RIRB Upper Address RIRB Write Pointer RIRB Response Interrupt Control RIRB Control RIRB Status RIRB Size Immediate Command Output Interface ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 232...
Page 233 128h Last Valid Index 12Ch FIFO Size 130h Stream Format 132h Buffer Descriptor Lower Base Address 138h Buffer Descriptor Upper Base Address 13Ch ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 233...
Page 234 Hardwired to “0”. Major Version – R – 8 bits - [Mem_Reg: Base + 03h] Field Name Bits Default Description Major Version Hardwired to 01h. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 234...
Page 235 Buffer. If “0”, Unsolicited Responses are accepted and dropped. Reserved 31:9 000000h Reserved. Software must do a read-modify-write to preserve the value of these bits. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 235...
Page 236 Output Stream Descriptor register. 00h: No Limit ( Stream size is limited only by Output Payload Capability register) 01h: 1 word payload FFh: 255 word payload ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 236...
Page 237 Interrupt Enable bit in the PCI Configuration Space. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 237...
Page 238 Address to be assigned on any 1 KB boundary. This register must not be written when the DMA engine is running or the DMA transfer may be corrupted. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 238...
Page 239 “0” from this bit to verify that the DMA engine is truly stopped. Reserved Reserved. Software must do a read-modify-write to preserve the value of these bits. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 239...
Page 240 Pointer to 0’s. The DMA engine must be stopped prior to resetting the Write Pointer or else DMA transfer may be corrupted. This bit will always be read as 0. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 240...
Page 241 RIRB Size Capability Hardwired to 4h indicating this controller only supports a RIRB size of 256 entries. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 241...
Page 242 DMA Position Lower Base Hardwired to 0. This forces 128-byte buffer alignment for Address Unimplemented cache line fetch optimizations. Bits ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 242...
Page 243 Controls whether an interrupt is generated when the Enable Descriptor Error Status is set. Reserved 15:5 000h Reserved. Software must do a read-modify-write to preserve the value of these bits. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 243...
Page 244 FIFO associated with this descriptor. 0000b = Reserved 0001b = Stream 1 1111b = Stream 15 ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 244...
Page 245 Bits Default Description Link Position in Buffer 31:0 00000000 This field indicates the number of bytes that have been received off the link. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 245...
Page 246 This value should not be modified except when the Run bit is “0”. Reserved 15:8 Reserved. Software must do a read-modify-write to preserve the value of these bits. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 246...
Page 247 011b = 4 (192 kHz, 176.4 kHz) 101b – 111b = Reserved Sample Base Rate 0 = 48 kHz 1 = 44.1 kHz Reserved Reserved ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 247...
Page 248 Bits Default Description Link Position in Buffer 31:0 00000000 An alias of the Link Position in Buffer register of each Alias Stream Descriptor. ©2008 Advanced Micro Devices, Inc. HD Audio Controllers Registers AMD SB600 Register Reference Manual Proprietary Page 248...
Page 249: Register Descriptions: Pci Bridges
IO/Mem Port Decode Enable Register 5 LPC Sync Timeout Count IO/Mem Port Decode Enable Register 6 Memory Range Register Rom Protect 0 ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 249...
Page 250 - the LPC bridge does not need to insert a wait state between the address and data on the AD lines. ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 250...
Page 251 Cache Line Size. Cache Line Size Register: This register specifies the system cache line size. This register is not implemented. ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 251...
Page 252 Parallel Port Enable 3 Port enable for parallel port, 678-67fh Parallel Port Enable 4 Port enable for parallel port, 3bc-3bfh ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 252...
Page 253 Port enable for Alternate super IO config port, 4e-4fh Configuration Port Enable Wide Generic IO Port Port enable for wide generic port, see register 64-65h Enable ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 253...
Page 254 This register defines a 4K byte memory range from {Base Address, 000h} to {Base Address, fffh}. The range is enabled by reg0x4A[4]. ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 254...
Page 255 This register contains two 16-bits of IO base address for LPC IO (wide generic port) target range. The limit address is found by adding 512 to the base address. ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 255...
Page 256 IDSEL for two 512 KB FWH memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD0 0000h-FFD7 FFFFh FF90 0000h-FF97 FFFFh ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 256...
Page 257 Default Description DMA_Enhance 1—Turn on the enhancement feature for the DMA function. This is for better bus efficiency 0—Enhancement off. ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 257...
Page 258 Tpm_amd This bit is replaced with strap pin K8system (to support AMD K8 CPU), and no longer in use. It is read only and returns 0. When the strap is 0, it ONLY supports these normal tpm cycles.
Page 259 BE PROGRAMMED FIRST BEFORE 84h, 88h, AND 8Ch ARE ACCESSED. TMKBC_Remap Register- RW - 16 bits - [PCI_Reg: 8Ch] Field Name Bits Default Description Reserved ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 259...
Page 260: Spi Rom Controller Registers
This is also useful for querying the SPI status and vendor_ID register. Register Name Offset Address SPI_Cntrl0 RestrictedCmd1 RestrictedCmd2 SPI_Cntrl1 SPI_CmdValue0 SPI_CmdValue1 SPI_CmdValue2 ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 260...
Page 261 Field Name Bits Default Description RestrictedCmd4 Same as RestrictedCmd0 RestrictedCmdWoAddr 15:8 Same as RestrictedCmd0 except this command does not have address ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 261...
Page 262 Note Either the SpiAccessMacRomEn and/or the SpiHostAccessRomEn bit is cleared. All of these registers become read only and cannot be changed. ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 262...
Page 263 This is used as the faked ID value to be returned to the MAC as a response to the RDID command. This is only used under the bridge mode. ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 263...
Page 264: Features Of The Lpc Block
ROM: supported address is in the range of 0000_0000h~ffff_ffffh • Firmware Hub Rom: supported address is in one of these two ranges: 000e_0000h~000f_ffffh, or ffb0_0000~ffff_ffffh ©2008 Advanced Micro Devices, Inc. LPC ISA Bridge (Device 20, Function 3) AMD SB600 Register Reference Manual Proprietary Page 264...
Page 265: Host Pci Bridge Registers (Device 20, Function 4)
Interrupt Pin Bridge Control Chip Control Diagnostic Control CLK Control Arbiter Control and Priority Bits SMLT Performance PMLT Performance PCDMA ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 265...
Page 266 Reserved PCI Command register Status- RW - 16 bits - [PCI_Reg: 06h] Field Name Bits Default Description Reserved Reserved ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 266...
Page 267 Header Type- R - 8 bits - [PCI_Reg: 0Eh] Field Name Bits Default Description Header Type Indicates the bridge is a multi-function device. Header type register ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 267...
Page 268 Read Only. Secondary Target Abort Signaled Target Abort on the secondary bus, write clears it. ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 268...
Page 269 Top 16 bits of the upper limit of 32-bit IO transactions. If the IO address decode mode bit (Regx48 bit[29] ) is clear then these bits will be zero ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 269...
Page 270 Primary Discard Timer Primary Discard Timer configuration, ‘0’ configures the timer to 15-bit, ‘1’ configures the timer to 10-bit. ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 270...
Page 271 Force secondary Parity Error Mode, ‘0’ disabled, ‘1’ enabled. Force Prim Parity Error Force primary Parity Error Mode, ‘0’ disabled, ‘1’ enabled. Diagnostic control register ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 271...
Page 272 Bits Default Description Reserved PCDMA Priority If enabled includes PCDMA request into high priority list Reserved Reserved Priority Bits ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 272...
Page 273 PCIB_Dual_EN_dn Enables decoding of Dual Address Cycle on secondary side for downstream memory transactions Reserved ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 273...
Page 274 PCI bus. The purpose of this register is to hide the device from OS 0—The corresponding IDSEL bit is masked 1—The corresponding IDSEL bit is not masked. ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 274...
Page 275 (depending on bit[2:0] in this register), the flush happens as soon as the cycle arrives at PCI bus. ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 275...
Page 276 1: Prefetch is disabled for upstream normal memory read (other than read line or read multiple). Also refer to reg0x40[4] and reg0x64[7]. Reserved 31:22 ©2008 Advanced Micro Devices, Inc. Host PCI Bridge Registers (Device 20, Function 4) AMD SB600 Register Reference Manual Proprietary Page 276...
Page 277: Register Descriptions: General Purpose Functions/Interrupt Controllers/Support Function Pins
1: SPKR 1: Input (Tri-state) GPIO3/ PM IO Reg60h[Bit 6] Reg80h[Bit 7] Reg81h[Bit 3] Reg80h[Bit 3] FAN0 0: GPIO 0: Output 1: Input (Tri-state) 1: FAN0 ©2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 277...
Page 278 1: Input (Tri-state) GPIO14/ SMBus Reg83h[Bit 5] Reg 82h[Bit 5] Reg 83h[Bit 1] Reg 82h[Bit 1] 0: ROM_RST# ROM_RST# 0: Output 1: GPIO 1: Input (Tri-state) ©2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 278...
Page 279 07h[Bit 4] SPDIF_OUT/ 0: GPIO or AC97 port 0: Output enable PCICLK7 1: PCICLK7 1: Input (Tri-state) PM IO Reg59h[Bit 0] 0: AC97 port 1: GPIO ©2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 279...
Page 280 1: Input (Tri-state) GPIO52/ PM2 IO Reg3Bh[Bit 0] Reg 50h[Bit 7] Reg 51h[Bit 3] Reg 50h[Bit 3] FANIN2 0: GPIO 0: Output 1: FANIN2 1: Input (Tri-state) ©2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 280...
Page 281 1: Input (Tri-state) GPIO73/ SMBus Reg5Bh[Bit 7] Reg 5Ah[Bit 7] Reg 5Bh[Bit 3] Reg 5Ah[Bit 3] GNT4# 0: GNT4# 0: Output 1: GPIO 1: Input (Tri-state) ©2008 Advanced Micro Devices, Inc. GPIO/GPOC AMD SB600 Register Reference Manual Proprietary Page 281...
Page 282: Gpoc
1–In this table, the “GPIO” portion of the pin name has been put at the front of the names for the sake of clarity, making the pin names different from how they appear in the AMD SB600 Databook. 2–Register A9h[7:0] is addressed as A8[15:8] in some AMD documents.
Page 283: Gevent/Gpe/Gpm/Extevent
GEVENT1/ SMBus PM IO PM IO ACPI PM IO KBRST# Reg64h[Bit9] Reg30h[Bit3:2] Reg36h[Bit 1] GPE04h[Bit 1] Reg39h[Bit 1] 0: KBRST# or ACPI GPE00h[Bit 1] 1: GEVENT1 ©2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 283...
Page 284 ACPI GPE00h[Bit20] GPM2/ SMBus PM IO PM IO ACPI PM IO USB_OC2# Reg64h[Bit 23] Reg33h[Bit3:2] Reg37h[Bit 5] GPE04h[Bit21] Reg3Ah[Bit 5] =1 to enable or ACPI GPE00h[Bit21] ©2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 284...
Page 285 0: GPM9 1: SLP_S2 EXTEVENT SMBus PM IO PM IO ACPI PM IO Reg64h[Bit 22] Reg32h[Bit1:0] Reg37h[Bit 0] GPE04h[Bit16] Reg3Ah[Bit 0] =1 to enable or ACPI GPE00h[Bit16] ©2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 285...
Page 286: Gpm As Gpio
4. Set CM Data register 0C51h Bits [7:6] = 00b to set GPM port for read. 5. Read the input status through port 0C52h. For GPM[9:8], simply read the input status from PM I/O 96h Bits [1:0]. ©2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 286...
Page 287: Gpm Pins As Output
Reg0Dh[Bit 2] Reg04h[Bit 0] Reg07h[Bit 0] Reg0Dh[Bit 0] EXTEVNT1#/ PM IO PM IO PM IO PM IO LPC_SMI# Reg0Dh[Bit 3] Reg04h[Bit 1] Reg07h[Bit 1] Reg0Dh[Bit 1] ©2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent AMD SB600 Register Reference Manual Proprietary Page 287...
Page 288: Thrmtrip/Talert
Polarity Control TALERT#/ PM IO SMI# IO C50h/C51h, index 03h IO C50h/C51h, index GPIO64/ Reg67h[Bit 5] [Bit 1]=1 02h [Bit 0] TEMPIN3 0=Active Low 1=Active High ©2008 Advanced Micro Devices, Inc. THRMTRIP/TALERT AMD SB600 Register Reference Manual Proprietary Page 288...
Page 289: Real Time Clock (Rtc)
Note: Some RTC RAM space can be protected from read/write if corresponding bits are set to 1 in RTCProtect register (PCI_Reg 6Ah). ©2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 289...
Page 290 The analog portion consists of two major parts: one is a 256-byte CMOS RAM and the other a 44-bit ripple counter. Register Name Offset Address Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Day of Week Date of Month Month Year ©2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 290...
Page 291 This register can be set by software (SET bit of Register B = 1) or can be automatically updated by hardware every hour. When set by software, hardware updating is disabled. ©2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 291...
Page 292 Register A - RW – 8 bits - [RTC_Reg: 0Ah] Field Name Bits Default Description Rate Selection(RS0) These four rate-selection bits select one of the 13 taps on the ©2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 292...
Page 293 If SET bit = 0, the Time Registers are updated every second. Register B: Control register Register C - R – 8 bits - [RTC_Reg: 0Ch] Field Name Bits Default Description Reserved ©2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 293...
Page 294 (SET bit of Register B = 1) or can be automatically updated by hardware every century. When set by software, hardware updating is disabled. Century Register ©2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 294...
Page 295 RTC RAM Enable - RW – 8 bits - [RTC_Reg: 7Fh] Field Name Bits Default Description RtcRamEnable Setting this bit will enable access to the RTC RAM Reserved 0000000b RTC RAM Enable register. ©2008 Advanced Micro Devices, Inc. Real Time Clock (RTC) AMD SB600 Register Reference Manual Proprietary Page 295...
Page 296: Ioxapic Registers
Write to this register will clear the remote IRR bit in the redirection table entry found matching the interrupt vector. This provides an alternate mechanism other than PCI special cycle for EOI to reach IOXAPIC. ©2008 Advanced Micro Devices, Inc. IOXAPIC Registers AMD SB600 Register Reference Manual Proprietary Page 296...
Page 297: Indirect Access Registers
0 – Edge 1 – Level Mask Mask the interrupt injection at the input of this device Write 0 to unmask Reserved 31:17 0000h Reserved 55:32 000000h ©2008 Advanced Micro Devices, Inc. IOXAPIC Registers AMD SB600 Register Reference Manual Proprietary Page 297...
Page 298 Redirection Table Entry [0–23] [Indirect Address Offset = 11/10H–3F/3EH] RW Field Name Bits Default Description Destination ID 63:56 Bits [19:12] of the address field of the interrupt message ©2008 Advanced Micro Devices, Inc. IOXAPIC Registers AMD SB600 Register Reference Manual Proprietary Page 298...
Page 299: Appendix A: Ac97 Audio Faqs
90. So the decision was made to move the two fields to the new register 0x8C. ©2008 Advanced Micro Devices, Inc. Appendix A: AC97 Audio FAQs AMD SB600 Register Reference Manual Proprietary Page 299...
Page 300: Appendix B: Revision History
Appendix B: Revision History Date Rev. Comment September, 2008 3.03 First release of the public version. ©2008 Advanced Micro Devices, Inc. Appendix B: Revision History AMD SB600 Register Reference Manual Proprietary Page 300...

AMD SB600 Technical Reference Manual

1 Introduction

2 Register Descriptions: PCI Devices

3 Register Descriptions: PCI Bridges

4 Register Descriptions: General Purpose Functions/Interrupt Controllers/Support Function Pins

Appendix A: AC97 Audio Faqs

Appendix B: Revision History

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