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Display Output Registers
Field Name
TMDSA_PLL_DEBUG
TMDSA_TX_DEBUG
Reserved for debugging purposes
Field Name
DVOA_ENABLE
DVOA_PIXEL_ENCODING
Field Name
DVOA_SOURCE_SELECT
DVOA_SYNC_SELECT
DVOA_STEREOSYNC_SELECT
Source Select control for Data, H/VSYNC & Stereosync
Field Name
DVOA_TRUNCATE_EN
DVOA_TRUNCATE_DEPTH
DVOA_SPATIAL_DITHER_EN
DVOA_SPATIAL_DITHER_DEPTH
DVOA_TEMPORAL_DITHER_EN
DVOA_TEMPORAL_DITHER_DEPTH
M56 Register Reference Manual
2-316
TMDSA_TRANSMITTER_DEBUG - RW - 32 bits - DISPDEC:0x7918
Bits
7:0
11:8
DVOA_ENABLE - RW - 32 bits - DISPDEC:0x7980
Bits
0
8
DVOA_SOURCE_SELECT - RW - 32 bits - DISPDEC:0x7984
Bits
0
8
16
DVOA_BIT_DEPTH_CONTROL - RW - 32 bits - DISPDEC:0x7988
Bits
0
4
8
12
16
20
Default
0x0
Drives ITPL pins on TMDSA macro
0x0
Drives ITX pins on TMDSA macro
Default
0x0
Enable for DVO
0=Disable
1=Enable
0x0
Selects pixel encoding format
0=RGB 4:4:4 or YCBCR 4:4:4
1=YCbCr 4:2:2
Default
0x0
Select between 1st and 2nd display streams
0=CRTC1 data is used
1=CRTC2 data is used
0x0
Select between SYNCA and SYNCB signals from CRTC
0=HSYNC_A & VSYNC_A from the selected CRTC are used
1=HSYNC_B & VSYNC_B from the selected CRTC are used
0x0
Select between CRTC1 and CRTC2 stereosync signals
0=DVOA Stereosync from CRTC1 used
1=DVOA Stereosync from CRTC2 used
Default
0x0
Enable bit reduction by truncation
0=Disable
1=Enable
0x0
Select truncation depth
0=18bpp
1=24bpp
0x0
Enable bit reduction by spatial (random) dither
0=Disable
1=Enable
0x0
Select spatial dither depth
0=18bpp
1=24bpp
0x0
Enable bit reduction by temporal dither (frame mod.)
0=Disable
1=Enable
0x0
Select temporal dither depth
0=18bpp
1=24bpp
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
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