AMD M56 Reference Manual page 128

VIP/I2C Registers
Field Name
VIPH_CH3_SCNT
Byte count of transfer requested.
Field Name
VIPH_CH0_ACNT (R)
Read back of remaining byte count.
Field Name
VIPH_CH1_ACNT (R)
Read back of remaining byte count.
Field Name
VIPH_CH2_ACNT (R)
Read back of remaining byte count.
Field Name
VIPH_CH3_ACNT (R)
Read back of remaining byte count.
Field Name
VIPH_CLK_SEL
VIPH_REG_RDY (R)
VIPH_MAX_WAIT
VIPH_DMA_MODE
VIPH_EN
VIPH_DV0_WID
M56 Register Reference Manual
2-122
Bits Default
19:0 0x0
VIPH_CH0_ABCNT - RW - 32 bits - VIPDEC:0xC30
Bits Default
19:0 0x0
VIPH_CH1_ABCNT - RW - 32 bits - VIPDEC:0xC34
Bits Default
19:0 0x0
VIPH_CH2_ABCNT - RW - 32 bits - VIPDEC:0xC38
Bits Default
19:0 0x0
VIPH_CH3_ABCNT - RW - 32 bits - VIPDEC:0xC3C
Bits Default
19:0 0x0
VIPH_CONTROL - RW - 32 bits - VIPDEC:0xC40
Bits Default
7:0 0x0
13 0x0
19:16 0x0
20 0x0
21 0x0
24 0x0
Description
Write non-zero byte count will trigger DMA. Maximum 2 jobs can be
loaded into the queue any one time.
Description
Keep track of active byte-count remaining.
Description
Keep track of active byte-count remaining.
Description
Keep track of active byte-count remaining.
Description
Keep track of active byte-count remaining.
Description
VIPH clock select, only even divider is permitted. Which means
VIPH_CLK_SEL(0) must be set to 1.
0=reserved
1=reserved
2=reserved
3=xclkby4
4=reserved
5=xclkby6
6=... (Only EVEN divider is permitted
0= VIPH is ready for next register access. 1= VIPH is busy for current
VIPH register access.
Number of VIP phases before issuing time out. Set to zero means no
time out
0= No DMA. 1= DMA
VIP Host port Enable
VIPH0 bus width
0=2-bit vipbus
1=4-bit vipbus
© 2007 Advanced Micro Devices, Inc.
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