Memory Controller Registers Sorted By Name - AMD M56 Reference Manual

A.9

Memory Controller Registers Sorted By Name

Table A-8 Memory Controller Registers Sorted by Name
MC_ARB_DRAM_PENALTIES
MC_ARB_DRAM_PENALTIES2
MC_ARB_DRAM_PENALTIES3
MC_ARB_RATIO_CLK_SEQ
MC_ARB_RDWR_SWITCH
MC_IO_A_PAD_CNTL_I0
MC_IO_A_PAD_CNTL_I1
MC_IO_CK_PAD_CNTL_I0
MC_IO_CK_PAD_CNTL_I1
MC_IO_CMD_PAD_CNTL_I0
MC_IO_CMD_PAD_CNTL_I1
MC_IO_DQ_PAD_CNTL_I0
MC_IO_DQ_PAD_CNTL_I1
MC_IO_QS_PAD_CNTL_I0
MC_IO_QS_PAD_CNTL_I1
MC_IO_RD_DQ_CNTL_I0
MC_IO_RD_DQ_CNTL_I1
MC_IO_RD_QS_CNTL_I0
MC_IO_RD_QS_CNTL_I1
MC_IO_RD_QS2_CNTL_I0
MC_IO_RD_QS2_CNTL_I1
MC_IO_WR_DQ_CNTL_I0
MC_IO_WR_DQ_CNTL_I1
MC_IO_WR_QS_CNTL_I0
MC_IO_WR_QS_CNTL_I1
© 2007 Advanced Micro Devices, Inc.
Proprietary
Register Name
AGP_BASE
AGP_BASE_2
MC_AGP_LOCATION
MC_ARB_MIN
MC_ARB_TIMERS
MC_CNTL0
MC_CNTL1
MC_DEBUG
MC_FB_LOCATION
MC_IMP_CNTL
MC_IMP_DEBUG
MC_IMP_STATUS
MC_IND_DATA
MC_IND_INDEX
MC_IO_PAD_CNTL
MC_IO_PAD_CNTL_I0
MC_IO_PAD_CNTL_I1
MC_IO_WR_CNTL_I0
MC_IO_WR_CNTL_I1
Address
MCIND:0x6
MCIND:0x7
MCIND:0x5
MCIND:0x13
MCIND:0x14
MCIND:0x15
MCIND:0x10
MCIND:0x16
MCIND:0x17
MCIND:0x12
MCIND:0x8
MCIND:0x9
MCIND:0xFE
MCIND:0x4
MCIND:0xA0
MCIND:0xA1
MCIND:0xA2
MCDEC:0x74
MCDEC:0x70
MCIND:0x92
MCIND:0x93
MCIND:0x8A
MCIND:0x8B
MCIND:0x8C
MCIND:0x8D
MCIND:0x8E
MCIND:0x8F
MCIND:0x82
MCIND:0x80
MCIND:0x81
MCIND:0x90
MCIND:0x91
MCIND:0x84
MCIND:0x85
MCIND:0x86
MCIND:0x87
MCIND:0x9C
MCIND:0x9D
MCIND:0x88
MCIND:0x89
MCIND:0x94
MCIND:0x95
MCIND:0x96
MCIND:0x97
M56 Register Reference Manual
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