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Table A-5 Display Registers Sorted by Name
DC_LUTB_WHITE_OFFSET_BLUE
DC_LUTB_WHITE_OFFSET_GREEN
DC_LUTB_WHITE_OFFSET_RED
DCP_LB_DATA_GAP_BETWEEN_CHUNK
DO_PERFCOUNTER0_SELECT
DO_PERFCOUNTER1_SELECT
DOUT_POWER_MANAGEMENT_CNTL
DVOA_BIT_DEPTH_CONTROL
DVOA_FORCE_OUTPUT_CNTL
© 2007 Advanced Micro Devices, Inc.
Proprietary
Register Name
DC_LUTB_CONTROL
DC_PAD_EXTERN_SIG
DC_REF_CLK_CNTL
DCO_PERFMON_CNTL_R
DCP_CRC_CONTROL
DCP_CRC_MASK
DCP_CRC_P0_CURRENT
DCP_CRC_P0_LAST
DCP_CRC_P1_CURRENT
DCP_CRC_P1_LAST
DISP_INTERRUPT_STATUS
DISP_TIMER_CONTROL
DMIF_CONTROL
DMIF_STATUS
DO_PERFCOUNTER0_HI
DO_PERFCOUNTER0_LOW
DO_PERFCOUNTER1_HI
DO_PERFCOUNTER1_LOW
DVOA_CONTROL
DVOA_CRC_CONTROL
DVOA_CRC_EN
DVOA_CRC_SIG_MASK1
DVOA_CRC_SIG_MASK2
DVOA_CRC_SIG_RESULT1
DVOA_CRC_SIG_RESULT2
DVOA_CRC2_SIG_MASK
DVOA_CRC2_SIG_RESULT
DVOA_ENABLE
DVOA_FORCE_DATA
DVOA_OUTPUT
DVOA_SOURCE_SELECT
(Continued)
Address
DISPDEC:0x6CC0
DISPDEC:0x6CD0
DISPDEC:0x6CD4
DISPDEC:0x6CD8
DISPDEC:0x7DCC
DISPDEC:0x7DD4
DISPDEC:0x7F18
DISPDEC:0x6C80
DISPDEC:0x6C84
DISPDEC:0x6C88
DISPDEC:0x6C90
DISPDEC:0x6C8C
DISPDEC:0x6C94
DISPDEC:0x6CBC
DISPDEC:0x7EDC
DISPDEC:0x7EF0
DISPDEC:0x6CB0
DISPDEC:0x6CB4
DISPDEC:0x7F04
DISPDEC:0x7F08
DISPDEC:0x7F00
DISPDEC:0x7F10
DISPDEC:0x7F14
DISPDEC:0x7F0C
DISPDEC:0x7EE0
DISPDEC:0x7988
DISPDEC:0x7990
DISPDEC:0x7998
DISPDEC:0x7994
DISPDEC:0x799C
DISPDEC:0x79A0
DISPDEC:0x79A4
DISPDEC:0x79A8
DISPDEC:0x79AC
DISPDEC:0x79B0
DISPDEC:0x7980
DISPDEC:0x79BC
DISPDEC:0x79B8
DISPDEC:0x798C
DISPDEC:0x7984
Page
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2-261
2-325
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2-339
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2-266
2-335
2-337
2-264
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2-336
2-317
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M56 Register Reference Manual
A-21
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