AMD M56 Reference Manual page 296

CRTC Registers
Field Name
D2CRTC_FRAME_COUNT (R)
Current frame count for CRTC2
Field Name
D2CRTC_VF_COUNT (R)
Current composite vertical and frame count for CRTC2
Field Name
D2CRTC_HV_COUNT (R)
Current composite H/V count of CRTC2
Field Name
D2CRTC_RESET_FRAME_COUNT (W)
Resets CRTC2 counters
Field Name
D2CRTC_HORZ_COUNT_BY2_EN
Controls the counters in CRTC2
D2CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE - RW - 32 bits - DISPDEC:0x68B8
Field Name
D2CRTC_MANUAL_FORCE_VSYNC_NEXT_LI
NE (W)
Manual force of VSYNC to happen next line
Field Name
D2CRTC_FORCE_VSYNC_NEXT_LINE_OCCU
RRED (R)
M56 Register Reference Manual
2-290
D2CRTC_STATUS_FRAME_COUNT - RW - 32 bits - DISPDEC:0x68A4
Bits
23:0
D2CRTC_STATUS_VF_COUNT - RW - 32 bits - DISPDEC:0x68A8
Bits
28:0
D2CRTC_STATUS_HV_COUNT - RW - 32 bits - DISPDEC:0x68AC
Bits
28:0
D2CRTC_COUNT_RESET - RW - 32 bits - DISPDEC:0x68B0
Bits
0
D2CRTC_COUNT_CONTROL - RW - 32 bits - DISPDEC:0x68B4
Bits
0
Bits
0
D2CRTC_VERT_SYNC_CONTROL - RW - 32 bits - DISPDEC:0x68BC
Bits
0
Default
0x0 Reports current frame count
Default
0x0 Reports current vertical and frame count
Default
0x0 Reports current horizontal and vertical count
Default
0x0 One-shot reset of frame counter of CRTC2 when written with '1'
Default
0x0 Enable the horizontal replication of 2. CRTC increments the H
counter every 2 pixel clocks
0 = disabled
1 = enabled
Default
0x0 One shot force VSYNCA to happen next line when written with '1'
Default
0x0 Reports whether force vsync next line event has occurred. Sticky bit.
0 = event has not occurred
1 = event has occurred
Description
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Description
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
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