AMD M56 Reference Manual page 29

Field Name
CK_DLY
CMD_DLY
ADR_DLY
Channel 1's delay line parameters clock/command/address bits
Field Name
PTERM
NTERM
PDRV
NDRV
RECV_DUTY
DRV_DUTY
PREAMP
SELFTIME
SLEW
VMODE
VREF_INT
VREF_INTR
Channel 0's clock pad control parameters
Field Name
PTERM
NTERM
PDRV
NDRV
RECV_DUTY
DRV_DUTY
PREAMP
SELFTIME
SLEW
VMODE
VREF_INT
VREF_INTR
Channel 1's clock pad control parameters
Field Name
PTERM
NTERM
PDRV
NDRV
RECV_DUTY
© 2007 Advanced Micro Devices, Inc.
Proprietary
MC_IO_WR_CNTL_I1 - RW - 32 bits - MCIND:0x89
Bits Default
4:0 0x0
9:5 0x0
14:10 0x0
MC_IO_CK_PAD_CNTL_I0 - RW - 32 bits - MCIND:0x8A
Bits Default
3:0 0x0
7:4 0x0
11:8 0x0
15:12 0x0
17:16 0x0
19:18 0x0
21:20 0x0
22 0x0
24:23 0x0
25 0x0
27:26 0x0
28 0x0
MC_IO_CK_PAD_CNTL_I1 - RW - 32 bits - MCIND:0x8B
Bits Default
3:0 0x0
7:4 0x0
11:8 0x0
15:12 0x0
17:16 0x0
19:18 0x0
21:20 0x0
22 0x0
24:23 0x0
25 0x0
27:26 0x0
28 0x0
MC_IO_CMD_PAD_CNTL_I0 - RW - 32 bits - MCIND:0x8C
Bits Default
3:0 0x0
7:4 0x0
11:8 0x0
15:12 0x0
17:16 0x0
Description
Clock delay
Command delay
Address delay
Description
NPL Termination control P side
NPL Termination control N side
NPL Drive control P side
NPL Drive control N side
Pad Receive Duty control
Pad Drive Duty control
NPL Pre-emphasis enable select, [1:0] for finger [7:6], 0=>disable,
1=>enable
Pad Pre-emphasis delay select
Pad slew rate control
Receive Default pull-up/down
Vref select
VrefR select
Description
NPL Termination control P side
NPL Termination control N side
NPL Drive control P side
NPL Drive control N side
Pad Receive Duty control
Pad Drive Duty control
NPL Pre-emphasis enable select, [1:0] for finger [7:6], 0=>disable,
1=>enable
Pad Pre-emphasis delay select
Pad slew rate control
Receive Default pull-up/down
Vref select
VrefR select
Description
NPL Termination control P side
NPL Termination control N side
NPL Drive control P side
NPL Drive control N side
Pad Receive Duty control
M56 Register Reference Manual
Memory Controller Registers
2-23