AMD M56 Reference Manual page 167

Field Name
MC_RBS_FORCE
MC_RBS_MAX_DYN_STOP_LAT
MC_RBS_CLOCK_STATUS (R)
MC_RBS_PROG_SHUTOFF
MC_RBS_PROG_DELAY_VALUE
MC_RBS dynamic clock gating control
Field Name
STARTUP_COUNTER
SYNCHRONIZER_COUNTER
DISPCLK_FUNC_SEL
SPARE
Miscellaneous control register
Field Name
TST_SRC_SEL
TST_REF_SEL
REF_TEST_COUNT
TST_RESET
TEST_COUNT (R)
PLL frequency measurement cntl
Field Name
SPARE_0
MRDCKA0_SOUTSEL
MRDCKA1_SOUTSEL
MRDCKB0_SOUTSEL
MRDCKB1_SOUTSEL
© 2007 Advanced Micro Devices, Inc.
Proprietary
MC_RBS_DYN_CNTL - RW - 32 bits - CLKIND:0x26
Bits Default
0 0x1
1 0x1
2 0x0
3 0x0
11:4 0x1
CG_MISC_REG - RW - 32 bits - CLKIND:0x1F
Bits Default
11:0 0x28
15:12 0x8
16 0x0
23:17 0x0
PLL_TEST_CNTL - RW - 32 bits - CLKIND:0x21
Bits Default
3:0 0x0
7:4 0x0
14:8 0x0
15 0x0
31:17 0x0
MCLK_MISC - RW - 32 bits - CLKIND:0x22
Bits Default
1:0 0x0
3:2 0x0
5:4 0x0
7:6 0x0
9:8 0x0
Description
0=Dynamic control CP sclk branch
1=Disable dynamic control of CP sclk branch
0=Programmable dynamic stopping latency
1=Max dynamic stopping latency
0=MC_RBS branch is off
1=MC_RBS branch is on
1=MC_RBS branch shutoff with PROG_DELAY_VALUE delay
Delay MC_RBS clock on/off by number of cycles
Description
Not used
Debug purpose, number of cycles to be used by clock switch logic
1=Use non functional display clock
Reserved
Description
Source clock to be measured
Clock used as a frequency reference
Run TST_REF_SEL by number of cycles
Reset frequency counter
Frequency output value
Description
Reserved
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
0=DLL output clock
1=QS pin
2=QS delayed 2 elements
3=QS delayed 4 elements
M56 Register Reference Manual
Clock Generator Registers
2-161