AMD M56 Reference Manual page 312

Display Output Registers
Field Name
DACB_BG_MODE
DACB_PWRCNTL
Field Name
TMDSA_ENABLE
TMDSA_ENABLE_HPD_MASK
TMDSA_HPD_SELECT
TMDSA_SYNC_PHASE
TMDSA_PIXEL_ENCODING
TMDSA_DUAL_LINK_ENABLE
TMDSA_SWAP
Field Name
TMDSA_SOURCE_SELECT
TMDSA_SYNC_SELECT
TMDSA_STEREOSYNC_SELECT
Source Select control for Data, H/VSYNC & Stereosync
Field Name
M56 Register Reference Manual
2-306
DACB_PWR_CNTL - RW - 32 bits - DISPDEC:0x7A68
Bits Default
1:0 0x0
17:16 0x0
TMDSA_CNTL - RW - 32 bits - DISPDEC:0x7880
Bits Default
0 0x0
4 0x0
8 0x0
12 0x1
16 0x0
24 0x0
28 0x0
TMDSA_SOURCE_SELECT - RW - 32 bits - DISPDEC:0x7884
Bits Default
0 0x0
8 0x0
16 0x0
TMDSA_COLOR_FORMAT - RW - 32 bits - DISPDEC:0x7888
Bits Default
Description
DACB bandgap macro configuration. Allows bandgap macro to be
configured to optimize performance.Goes directly to DAC
BG_MODE[1:0] input.
DACB bias current level control. Allows analog bias current levels to
be adjusted for performance vs. power consumption tradeoff.Goes
directly to DAC PWRCNTL[1:0] input.
Description
Enable for the reduction/encoding logic
0=Disable
1=Enable
0:Disallow
1:Allow override of TMDSA_ENABLE by HPD on disconnect
0=Result from HPD circuit can not override TMDSA_ENABLE
1=Result from HPD circuit can override TMDSA_ENABLE on dis-
connect
Select which hot plug detect unit to use for TMDSA. This selection is
only relevant if one of the HPD mask bits in this and other registers is
enabled.
0=Use HPD1
1=Use HPD2
Determine whether to reset phase signal on frame pulse
0: don't reset
1: reset
0=RGB 4:4:4 or YCBCR 4:4:4
1=YCbCr 4:2:2
Enable dual-link
0=Disable
1=Enable
Swap upper and lower data channels
0=Disable
1=Enable
Description
Select between display stream 1 & display stream 2
0=CRTC1 data is used
1=CRTC2 data is used
Select between SYNCA and SYNCB signals
0=HSYNC_A & VSYNC_A from the selected CRTC are used
1=HSYNC_B & VSYNC_B from the selected CRTC are used
Select between CRTC1 and CRTC2 stereosync signals
0=CRTC1 STEREOSYNC used
1=CRTC2 STEREOSYNC used
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary