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Field Name
F1_PMI_POWER_STATE
F1_PMI_PME_EN (R)
F1_PMI_DATA_SELECT (R)
F1_PMI_DATA_SCALE (R)
F1_PMI_PME_STATUS (R)
Power Management Status/Control Register
Field Name
F1_B2_B3_SUPPORT
F1_BPCC_EN
Power Management Bridge Support Extensions (BSE)
Field Name
F1_PMI_DATA
Power Management Data Register
Field Name
F1_CAP_ID
F1_NEXT_PTR
The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 2.3 configuration space capability list.
Field Name
F1_VERSION
F1_DEVICE_TYPE
F1_INT_MESSAGE_NUM
The PCI Express Capabilities register identifies PCI Express device type and associated capabilities.
Field Name
F1_MAX_PAYLOAD_SUPPORT
F1_PHANTOM_FUNC
F1_EXTENDED_TAG
F1_L0S_ACCEPTABLE_LATENCY
F1_L1_ACCEPTABLE_LATENCY
F1_ATTN_BUTTON_PRESENT
© 2007 Advanced Micro Devices, Inc.
Proprietary
F1_PMI_STATUS - RW - 16 bits - [CFGF1_DEC:0x54] [HIDEC:0x5454]
Bits
1:0
8
12:9
14:13
15
F1_PMI_BSE - R - 8 bits - [CFGF1_DEC:0x56] [HIDEC:0x5456]
Bits
6
7
F1_PMI_DATA - R - 8 bits - [CFGF1_DEC:0x57] [HIDEC:0x5457]
Bits
7:0
F1_PCIE_CAP_LIST - R - 16 bits - [CFGF1_DEC:0x58] [HIDEC:0x5458]
Bits
7:0
15:8
F1_PCIE_CAP - R - 16 bits - [CFGF1_DEC:0x5A] [HIDEC:0x545A]
Bits
3:0
7:4
13:9
F1_DEVICE_CAP - R - 32 bits - [CFGF1_DEC:0x5C] [HIDEC:0x545C]
Bits
2:0
4:3
5
8:6
11:9
12
Default
0x0
Power State
0x0
PME Enable
0x0
Data Select
0x0
Data Scale
0x0
PME Status
Default
0x0
0=B2/B3 Support for D3Hot
0x0
0=Bus Power/Clock Control Enable
Default
0x0
Power Management Data Register
Default
0x10
10=PCI Express capable
0x0
Next Capability Pointer -- The offset to the next PCI capability struc-
ture or 00h if no other items exist in the linked list of capabilities.
Default
0x1
0=PCI Express Capabilities Version
0x0
0=PCI Express Endpoint
0x0
Interrupt Message Number.
Default
0x0
0=128B size
0x0
0=No Phantom Functions
0x0
0=8 Bit Tag Supported
0x0
This field indicates the acceptable total latency that an Endpoint can
withstand due to the transition from L0s state to the L0 state.
0x0
This field indicates the acceptable latency that an Endpoint can with-
stand due to the transition from L1 state to the L0 state.
0x0
0=Attention Button Present
Bus Interface Registers
Description
Description
Description
Description
Description
Description
M56 Register Reference Manual
2-77
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