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Bus Interface Registers
PCIE_ADV_ERR_CAP_CNTL - RW - 32 bits - [CFGF0_DEC:0x118] [HIDEC:0x5118]
Field Name
FIRST_ERR_PTR (R)
ECRC_GEN_CAP (R)
ECRC_GEN_EN
ECRC_CHECK_CAP (R)
ECRC_CHECK_EN
Advanced Error Capabilities and Control Register
Field Name
TLP_HDR
Header Log Register captures the Header for the TLP corresponding to a detected error;
Field Name
TLP_HDR
Header Log Register
Field Name
TLP_HDR
Header Log Register
Field Name
TLP_HDR
Header Log Register
Field Name
F1_VENDOR_ID
Vendor ID register.
Field Name
F1_DEVICE_ID
Device ID register.
M56 Register Reference Manual
2-72
Bits
4:0
5
6
7
8
PCIE_HDR_LOG0 - R - 32 bits - [CFGF0_DEC:0x11C] [HIDEC:0x511C]
Bits
31:0
PCIE_HDR_LOG1 - R - 32 bits - [CFGF0_DEC:0x120] [HIDEC:0x5120]
Bits
31:0
PCIE_HDR_LOG2 - R - 32 bits - [CFGF0_DEC:0x124] [HIDEC:0x5124]
Bits
31:0
PCIE_HDR_LOG3 - R - 32 bits - [CFGF0_DEC:0x128] [HIDEC:0x5128]
Bits
31:0
F1_VENDOR_ID - R - 16 bits - [CFGF1_DEC:0x0] [HIDEC:0x5400]
Bits
15:0
F1_DEVICE_ID - R - 16 bits - [CFGF1_DEC:0x2] [HIDEC:0x5402]
Bits
15:0
Default
0x0
The First Error Pointer is a read-only register that identifies the bit
position of the first error reported in the Uncorrectable Error Status
register.
0x0
This bit indicates that the device is capable of generating ECRC
0x0
This bit when set enables ECRC generation. Default value of this
field is 0.
0x0
This bit indicates that the device is capable of checking ECRC
0x0
This bit when set enables ECRC checking. Default value of this field
is 0.
Default
0x0
TLP Header 1st DW
Default
0x0
TLP Header 2nd DW
Default
0x0
TLP Header 3rd DW
Default
0x0
TLP Header 4th DW
Default
0x1002
This field identifies the manufacturer of the device.
Default
0x0
This field identifies the particular device. This identifier is allocated by
the vendor.
Description
Description
Description
Description
Description
Description
Description
© 2007 Advanced Micro Devices, Inc.
Proprietary
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